Phase locked loop based FM transmitter

[dumindu89]

I am going to design a FM modulator based on digital phase locked loop as my final year project. Mainly the FM modulator. The modulator should be programmable to generate FM carrier frequencies in 100 kHz steps. Transmission frequency range: 88MHz - 108 MHz. There should not be interferences between each channel.

Here is the basic block diagram
**broken link removed**

Here I am going to use 74HC4046A IC for the digital phase locked loop and 74HC4059 IC for the programmable divided by N counter. Since the 74HC4046A Ic not working in the FM broadcasting band, a bandpass filter will be used to filter out the desired frequency range from the produced harmonics at the VCO.

I have few questions.

1. What are the benefits/advantages of using digital phase locked loop for FM modulation?
2. Is it possible to use the 74HC4046A IC for the design? What things should I consider?
3. How do I make the 74HC4059 IC as programmable to select the desired chaneel?
4. What are the other yhings I should concentrate when I designing this?

 

[chuckey]

4. The linearity of the VCO, FM broadcasts should have ~ .1% THD from mic to loudspeaker!!
Frank

 

[biff44]

You aren't going to get much transmit power that way. I would use a MAX2066 as the VCO.

Also, remember to lowpass filter the analog input above 15 KHz, or strange things will happen in a standard FM receiver.

 

[RF_Jim]

I am going to design a FM modulator based on digital phase locked loop as my final year project. Mainly the FM modulator. The modulator should be programmable to generate FM carrier frequencies in 100 kHz steps. Transmission frequency range: 88MHz - 108 MHz. There should not be interferences between each channel.

Here is the basic block diagram
**broken link removed**

Here I am going to use 74HC4046A IC for the digital phase locked loop and 74HC4059 IC for the programmable divided by N counter. Since the 74HC4046A Ic not working in the FM broadcasting band, a bandpass filter will be used to filter out the desired frequency range from the produced harmonics at the VCO.

I have few questions.

1. What are the benefits/advantages of using digital phase locked loop for FM modulation?
2. Is it possible to use the 74HC4046A IC for the design? What things should I consider?
3. How do I make the 74HC4059 IC as programmable to select the desired chaneel?
4. What are the other yhings I should concentrate when I designing this?

I wonder, how are you going to accomplish low-frequency modulation of any program material if that low-frequency audio material lies within the phase locked loop low pass filter bandwidth?

Applying low frequency audio signal directly into the VCO with an AC coupling cap, one is going to be 'fighting' the effects out of the phase comparator with the design shown above.

Jim

 

[biff44]

We were assuming he knows that he will need a < 100 Hz loop bandwidth in the PLL. FM receivers do not work at low frequencies, so he can throw away the 20 Hz to 100 Hz range with some impunity.

 

[betwixt]

I agree with Jim.

There should be a LPF at the output of the phase comparator otherwise three problems will occur. 1 - digital 'noise' from the comparator will feed back into the loop and 2 - the audio input will attenuate the control voltage and 3 - as pointed out by Jim, the PLL will do it's best to cancel the modulation because it will see the audio as being a deviation from correct frequency and try to correct it.

Answering the other question, just set a binary number at the input of the 74HC4059. If within achievable range, the output will be that number multiplied by the reference frequency.

Brian.

 

[thylacine1975]

Hi all

Dumindu - I designed a simple phase locked FM transmitter I used for teaching purposes about 10 years ago that you're welcome to:


It's dated by the IC's - both the National Semi LMX2337 and the Microchip PICF84 are getting old now, but they're certainly still available. I recall redesigning the PLL to use the more modern LMX2306 and PC16F628 a few years later, (but I'll have to find where I hid the files... but the oscillator/amplifier remained unchanged.

The three unused LM324 op-amps really bugged me, so I used it as an excuse to add stereo transmission functionality (add add a gazillion more parts in the process!) and wrap it around the existing PLL/oscillator. Oh, and increase the RF power output well beyond legal levels! (all in the name of teaching, of course It certainly works, but alas chuckey, I wouldn't vouch for its hi-fi-edness!


In both cases, the code within the PIC16F84 simply programmed the PLL registers according to the desired frequency set on the DIP switches. Apologies for the verbose code attachment, but here it is for the interested reader:

---

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/*****************************************************************************/
/* FM-PLL.c                                                                  */
/*                                                                           */
/* This program monitors the state of the DIP switch on the PLL PCB, sending */
/* new config data to the LMX2337 PLL IC when the switch value is changed.   */
/*                                                                           */
/* The output frequency = 88.1 + (DIP switch) x 0.1 MHz (to a max. of 107.9) */
/*                                                                           */
/*****************************************************************************/
 
#include <pic.h>                /* PIC details, selected by compiler options */ 
 
__CONFIG(PROTECT|FOSC1|FOSC0);  /* RAM prot(for 16f/c84),RC osc, no watchdog */
 
#define slatch RA0              /* Latch enable control signal to PLL        */
#define sdata  RA1              /* Serial data to LMX2337 PLL                */
#define sclk   RA2              /* Serial clock to LMX2337 PLL               */
 
 
void writeSynthesiserWord (unsigned long configWord)
  {
  unsigned char i=21;
 
  slatch = 0;                   /* Low -> LE to signify start of config data */
  do {
     sclk = 0;
     sdata = (configWord >> i) & 0x1;  /* Send data MSB (Bit 21) first       */
     sclk = 1;                         /* Toggle sclk to clock in data bit   */
     } while (i-- != 0);    
  slatch = 1;                   /* Latch 22 bit word into the PLL            */
  }
  
 
void updateSynthesiser (unsigned char controlByte)
  {
  unsigned long a, b;           /* A & B correspond to the LMX2337 registers */
  unsigned long totalDivisor, Fout, outputWord;
  
  Fout = 881L + controlByte;
  if (Fout > 1079)              /* Limit output frequency to 107.9 MHz       */
     Fout = 1079;
     
  totalDivisor = 5L*Fout;
  a = totalDivisor & 0x3F;
  b = totalDivisor >> 6;
  outputWord = (b << 9) | (a << 2) | 0x1;           /* Compile RF2 divisor   */
 
  writeSynthesiserWord(outputWord);
  }
 
 
void initialiseSynthesiser (unsigned char initialValue)
  {
  /* Program RF1 */
  writeSynthesiserWord(0x080002);     /* Set R divisor                       */
  writeSynthesiserWord(0x200003);     /* Set A & B and disable RF1           */
 
  /* Program RF2 */
  writeSynthesiserWord(0x1607D0);     /* Set R div=500, Icp=5mA, FoLD=RF2 LD */
  updateSynthesiser(initialValue);    /* Write initial values of A & B       */
  }
 
 
void main (void)
  {
  unsigned char switchValue;
  unsigned char lastSwitchValue;
 
  RBPU  = 0;                    /* Enable weak pull-ups for PORTB inputs     */
  TRISA = 0x0;                  /* All PORTA bits configured as outputs      */
  TRISB = 0xFF;                 /* All PORTB bits configured as inputs       */
 
  initialiseSynthesiser(PORTB); /* Set configuration registers of the PLL    */
 
  while (1) {
     switchValue = PORTB;       /* Read binary word from the DIP switch      */
     
     if (switchValue != lastSwitchValue) {
        updateSynthesiser (switchValue);  
        lastSwitchValue = switchValue;
        }
     }
  }

---

I could locate my (handwritten) design notes if you're interested - just let me know. Otherwise, have fun experimenting!

 

[sky_123]

For something more challenging, you could consider DDS based device - someone here has done this, looks like an interesting project:
**broken link removed**
The design could be improved - e.g. not use the DDS to directly generate 88MHz, which would be slightly spurious!

 

[G0HZU]

I have few questions.

1.What are the benefits/advantages of using digital phase locked loop for FM modulation?
2.Is it possible to use the 74HC4046A IC for the design? What things should I consider?
3.How do I make the 74HC4059 IC as programmable to select the desired chaneel?
4.What are the other yhings I should concentrate when I designing this?

Answers:
1. Good frequency accuracy and stability over time and temperature and ease of tuning across multiple channels.
2. Yes you can use the 4046. Consider which phase detector you are going to use within the device and if you want to use an active LPF after it. However, see answer 3 below.
3. I think your block diagram has a problem with the 4059 as I don't think it is fast enough to be clocked at the VCO frequency of 88-108MHz. So your proposed system won't work.
4. You might want to consider adding a frequency display (LCD or LED) and a small MCU chip to provide the user interface. Also, are you going to use SMD components and if so you need to consider how you will make your PCB.

Because the 4059 divider won't work at 88-108MHz you should consider using a modern PLL chip containing the divider, phase detector etc. This can be controlled by the same MCU chip (AVR/PIC) that drives the display and accepts inputs from up/down tune buttons.

 

[dumindu89]

Answers:
I think your block diagram has a problem with the 4059 as I don't think it is fast enough to be clocked at the VCO frequency of 88-108MHz. So your proposed system won't work.

I am just going to get the VCO maximum output frequency =< 40MHz by changing the external resistor (R1) and capacitor (C1) of the 4046A and get the output in 88MHz - 108MHz not from the basic frequency but from the produced harmonics as the VCO output. Will it still be a problem for the 4059 IC?

4. You might want to consider adding a frequency display (LCD or LED) and a small MCU chip to provide the user interface. Also, are you going to use SMD components and if so you need to consider how you will make your PCB.

SMD? :O But I found a DIP-16 package for 4046A.

Because the 4059 divider won't work at 88-108MHz you should consider using a modern PLL chip containing the divider, phase detector etc. This can be controlled by the same MCU chip (AVR/PIC) that drives the display and accepts inputs from up/down tune buttons.

If you can provide a good modern IC number which is suitable for this, it will be a great help. I searched for such ICs, but all of them are coming with SMT packaging. :-(

We were assuming he knows that he will need a < 100 Hz loop bandwidth in the PLL. FM receivers do not work at low frequencies, so he can throw away the 20 Hz to 100 Hz range with some impunity.

No, I don't know about it. Can you mention any recommended referance to study about it?

I agree with Jim.

There should be a LPF at the output of the phase comparator otherwise three problems will occur. 1 - digital 'noise' from the comparator will feed back into the loop and 2 - the audio input will attenuate the control voltage and 3 - as pointed out by Jim, the PLL will do it's best to cancel the modulation because it will see the audio as being a deviation from correct frequency and try to correct it.

Answering the other question, just set a binary number at the input of the 74HC4059. If within achievable range, the output will be that number multiplied by the reference frequency.

Brian.

Mmm.. I am touching to this field in depth for the first time. Therefore bit hard to recognise how these problems occur. Anyway thanks for the information.

4. The linearity of the VCO, FM broadcasts should have ~ .1% THD from mic to loudspeaker!!
Frank

Can you briefly explain about this condition?

 

[G0HZU]

Whoops, I just realised you are intending to use the VCO inside the 4046 and pick out a harmonic. (I thought you were just using the phase detector section of this chip)
Using the 4046 VCO is a bad idea for lots of reasons. One reason is that each time you multiply by 2 you degrade the phase noise by 6dB.

With a 4046 you would have to multiply by 10 and this would mean a 20dB degradation. Also, you would need to heavily filter the output to suppress unwanted harmonics of the VCO.

Also, you would have to synthesise in 10kHz steps to get 100kHz steps meaning the PLL divider noise will be high. The VCO inside the 4046 will be noisy anyway so this really isn't a good approach.

If SMD is not allowed you could use something like a Motorola MC145152-2 PLL IC in DIL package with a dual modulus (div 16/17) prescaler (eg Fujitsu MB503) but these DIL parts are old and hard to obtain. You would also have to make your own VCO at 100MHz but this isn't really that difficult even if you use leaded parts rather than SMD.

 

[dumindu89]

Whoops, I just realised you are intending to use the VCO inside the 4046 and pick out a harmonic. (I thought you were just using the phase detector section of this chip)
Using the 4046 VCO is a bad idea for lots of reasons. One reason is that each time you multiply by 2 you degrade the phase noise by 6dB.

With a 4046 you would have to multiply by 10 and this would mean a 20dB degradation. Also, you would need to heavily filter the output to suppress unwanted harmonics of the VCO.

Also, you would have to synthesise in 10kHz steps to get 100kHz steps meaning the PLL divider noise will be high. The VCO inside the 4046 will be noisy anyway so this really isn't a good approach.

If SMD is not allowed you could use something like a Motorola MC145152-2 PLL IC in DIL package with a dual modulus (div 16/17) prescaler (eg Fujitsu MB503) but these DIL parts are old and hard to obtain. You would also have to make your own VCO at 100MHz but this isn't really that difficult even if you use leaded parts rather than SMD.

Ohh.. That's a bad news for me.
Is there any VCO in 74 series which suitable for my project?

I have another, question. What is the traditional/conventional method of FM transmitter design instead of using PLL?

 

[sky_123]

You need some sort of frequency stability, so you do need a PLL or some other method. Low cost FM transmitters just use a VCO, no PLL, and directly modulate using the VCO.
Is this a university project? If so, the VCO-only method is pretty uninspiring, why not do something challenging like PLL or better still improve on the DDS based method like the link I described above.

 

[G0HZU]

Don't take this the wrong way but I also think you may need to reconsider your choice of project. IMO your project should ideally satisfy a valid requirement. In 2012 I don't think basic FM modulator is a good choice. It was maybe a VERY good choice 20-30 years ago especially if it was designed with discrete parts with design info for each section.

However, if you do want to stick with an FM modulator then maybe you should draw up a set of sub requirements or goals that your project has to meet.
i.e. freq range, accuracy, drift, phase noise, lock time (for a PLL), power consumption, deviation, AF response etc, power output are a few basic ones to start you off.

Without these goals you can't really guage your success and it's also difficult for people to advise you if they don't know the design goals?

---------- Post added at 19:18 ---------- Previous post was at 19:11 ----------

Is this a university project? If so, the VCO-only method is pretty uninspiring, why not do something challenging like PLL or better still improve on the DDS based method like the link I described above.

I agree. A few years ago I designed a stereo modulator and did it all in a cheap MCU chip. It required some very efficient code to do everything within the alloted sample period (i.e. not many MCU clock periods are available per sample to read both ADC channels and do the modulation and add the pilot tone and then send out the modulated signal)

 

[biff44]

Did you bother to look up the maxim part number?

 

[RCinFLA]

You will need a very stable VCO. With very low loop bandwidth to prevent modulation from being erased by PLL you will have no PLL help in removing any mechanical microphonics induced on the VCO.

You might also look at two port modulation. The principle is to modulate the reference and the VCO in just the right ratio such the phase detector see little net difference. The messy part is as the main VCO divider is changed to change frequency, the delta F on the phase detector changes modulation gain tracking therefore the injected modulation to the reference must also change. You may also find the AC modulation sensitivity of the VCO changes versus frequency of VCO (which also is a problem for your original proposal).

 

[biff44]

BTW Thylacine1975 points out to me that I gave you a bum Maxim part number. Try the MAX2606.

 

[dumindu89]

BTW Thylacine1975 points out to me that I gave you a bum Maxim part number. Try the MAX2606.

Hmm.. packaging of MAX2606 is surface mounting. However let me think about that IC again. :smile:

Whoops, I just realised you are intending to use the VCO inside the 4046 and pick out a harmonic. (I thought you were just using the phase detector section of this chip)
Using the 4046 VCO is a bad idea for lots of reasons. One reason is that each time you multiply by 2 you degrade the phase noise by 6dB.

With a 4046 you would have to multiply by 10 and this would mean a 20dB degradation. Also, you would need to heavily filter the output to suppress unwanted harmonics of the VCO.

Also, you would have to synthesise in 10kHz steps to get 100kHz steps meaning the PLL divider noise will be high. The VCO inside the 4046 will be noisy anyway so this really isn't a good approach.

If SMD is not allowed you could use something like a Motorola MC145152-2 PLL IC in DIL package with a dual modulus (div 16/17) prescaler (eg Fujitsu MB503) but these DIL parts are old and hard to obtain. You would also have to make your own VCO at 100MHz but this isn't really that difficult even if you use leaded parts rather than SMD.

I may use separate ICs for VCO and Phase detector. No problem. :smile:

 

[dumindu89]

Hmm... I should use a external inductance with MAXIM 2606 which is not easy to make a coil with accurate inductance and I found the following statement in this site and bit confused about it. Is it true? https://www.radiolocman.com/shem/schematics.html?di=64466

although the frequency can only be varied by approximately ±3 MHz around the midrange frequency set by the coil L

sn74s124 is my current choice and the disadvantage is, I need the 2nd harmonic to get the signal in FM broadcasting band.
Any comments on my current choice?

Are there any other VCO ICs that suits my requirements?

 

[sky_123]

The maxim ic will be the easiest VCO. A coil can be made using maths, no need to measure the inductance precisely. You'll most likely need to use a coil with any VCO ic that you use, so you can't get away from that requirement.
Otherwise, you could create a single-transistor oscillator with a coil, but probably for a first VCO the maxim is the way to go, since there is lots of information in the data sheet. It is surface mount, but not super-tiny, so as long as you have a reasonably small (inexpensive) soldering iron you'll be fine. Also, the data sheet shows that you can tune far more than 3MHz (see the chart on page 5 of the data sheet), and easily accomodate the entire FM band. I've not used the maxim device however.