Where do I get the osu025_stdcells.lib from? problm using Encounter RTL Compiler.

[jaishankar]

Hello,

This is a beginner question. Please help!!!

There is Encounter RTL Compiler - physical (version 10.1.302) tool available in my university.
I need to learn the tool and develop a microprocessor- starting from verilog code to the final physical layout. - no one else is using the software in my univ. I had to learn on my own.

For now, to get familiarized with the tool, I am asked to do a simple design with a few gates.
I am following tutorials from other universities. - but couldn't get a good understanding of the tool. (I have done full custom IC designs in the last semester using cadence virtuoso, but I have no knowledge in design automations - like the Encounter tools.)
one of the tutorials I got is this.. **broken link removed**

Now my doubts are..

1. We have Nangateopencelllibrary. like NangateOpenCellLibrary_functional.lib installed in our systems., I just used this library file in RTL compiler. I run the code , but I see a "synthesis failed" message in the terminal, (I do see some gate structure/circuit diagram in the result window). What should I do to synthesise a verilog code properly? (the verilog code I used is this.. (from the tutorial)

module accu(in, acc, clk, reset);
input [7:0] in;
input clk, reset;
output [7:0] acc;
reg [7:0] acc;

always @(posedge clk)
begin
if (reset) acc<=0;
else acc<=acc+in;
end

endmodule

The error message I get is this..
Error : Cannot perform synthesis because libraries do not have usable inverters. [LBR-171] [synthesize]
: Inverters are required for mapping. Ensure that the loaded libraries contain at least one usable inverter.
Error : Cannot perform synthesis because libraries do not have usable basic gates. [LBR-172] [synthesize]
: At least one usable two-input and/or/nand/nor gate (modulo inversion at inputs) is required for mapping. Ensure that the loaded libraries contain at least one such cell.
Synthesis failed.
Error sourcing '/eng/home/jaishank/tutfirst/synthesis/rtl.tcl'.


2. In the tutorial, they've used a Osu stdcell library, where do I get these open source libraries from? I have to do a simple example design for now, I would be happy if you can suggest me a good library, and some tutorial/guidance on how to use them.
Please help !!

 

[tariq786]

I think it might be a path problem. Somehow the tool is not able to find out the location of the library. Are you sure you have given the library path and the tool is aware of where the library is?

If not, then use the osu_free_library. Its the simplest one i know of. See attachment

 

[englishdogg]

jaishankar,

To my knowledge of RTL Compiler, the reason your getting an Error is because your library does not have a single usable inverter and any 2 input combo cell to implement the logic during synthesis. This is required if your doing synthesis with RC - atleast one inverter and one basic 2 input combo cell.

Also it could be that the library carries the libcell but you may have marked it a set_dont_use.

 

[jaishankar]

Hello,
Thanks for your reply. I have actually used FreePDK45nm library and it is working fine. I still don't know the reason why nangate library didn't work,, I did check the nangate library, ----- inverters, AND/OR gates and all basic gates were available.
I am clueless why those gates were not recognized.

Can you tell me how can I improve my knowledge in utilzing these software tools?

Thank you all.

 

[englishdogg]

You can try using the check_library command to identify why the libcells were not available or also look for Warnings once you have loaded the library.
In RC there is an option of "write_template <options>" use this command to create a script as a start for the synthesis flow you wish to execute. Try and explore and see what each command does... rest will come with curiosity and as more and often you play with your design.

 

[jaishankar]

Thank you. I haven't yet completed a simple example design. I want to see the whole flow in the tool RTL Compiler - Physical.
Logic synthesis is done.
Now, I have a couple of doubts.
1. The timing information offered in the library FreePDK,-- ".tlf" file is not accepted in the RTL compiler - Physical. What should I use for importing the timing information then???
2. I don't know how to start with the floorplanning. I have to do everything via script file in this software, But "floorplan" syntax is not working., may be I got to create a .def file now.
3. How do I create a .def file? Can Someone tell me how can I educate myself on creating a correct script file which gives me the correct physical layout.



How can I learn the proper scripting/ learn the tool? plz share your ideas.

 

[englishdogg]

1. ".tlf" is not supported in RTLC, you can use SDC or RTLC native SDC commands
2. RTLC will not floorplanning for you - you nee dto use a PnR tool Cadence EDI or Synopsis ICC many more available. Yes, RTLC accepts .def file
3. Ditto as point "2" you will need to use PnR tools to genertae the .def file

Scripting - you may want to check these links
https://www.edaboard.com/threads/25071/
https://www.edaboard.com/threads/27350/
https://www.edaboard.com/threads/237476/

Hope this helps...