BartlebyScrivener
Member level 5
Hi all, I am very new to digital design and verilog so this might be quite simple....
Is there any way I can write the condition.
x does not equal 'any multiple of' Y
it is the 'any multiple of' I am unsure about. I am making a paramatised 2D mesh of router modules and want to ensure the routers at the edge of the mesh do not look for inputs where there is not one.
Also, I am writing a network-on-chip, it is the first thing I have designed and written and I dont have a teacher, can I just post the whole lot on here once I am done for a critique?
Thankyou1
Is there any way I can write the condition.
x does not equal 'any multiple of' Y
it is the 'any multiple of' I am unsure about. I am making a paramatised 2D mesh of router modules and want to ensure the routers at the edge of the mesh do not look for inputs where there is not one.
Also, I am writing a network-on-chip, it is the first thing I have designed and written and I dont have a teacher, can I just post the whole lot on here once I am done for a critique?
Thankyou1