Explain vhdl ligne " conv_std_logic_vector(CONV_INTEGER(cnt)"

[omar-malek]

hi to all .

Can any one explain me this ligne in the code of counter

cnt <= conv_std_logic_vector(CONV_INTEGER(cnt) + 1, width);
thank you.

ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity COUNTERCLR is
generic (
width : integer := 8);

port (
clk : in std_logic;
rst_n : in std_logic;
en : in std_logic;
clear : in std_logic;
outcnt : out std_logic_vector(width-1 downto 0));
end COUNTERCLR;

architecture COUNTERCLR1 of COUNTERCLR is

signal cnt : std_logic_vector(width-1 downto 0);

begin -- COUNTERCLR1

process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
cnt <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if en = '1' then
cnt <= conv_std_logic_vector(CONV_INTEGER(cnt) + 1, width);---- CONV_STD_LOGIC_VECTOR(integer, bits)
elsif clear = '1' then
cnt <= (others => '0');
end if;

end if;
end process;

outcnt <= cnt;

end COUNTERCLR1;

 

[TrickyDicky]

Its adding one to cnt. Its a bit of a crappy way to do it though, and uses non-standard VHDL.

 

[Arindam123]

if you dont give the enable signal, it wont work. generally its adding 1 to the count only after the enable signal is set to 1.

 

[FvM]

Its adding one to cnt. Its a bit of a crappy way to do it though, and uses non-standard VHDL.

Yes. The curious thing is that the construct isn't necessary at all when using STD_LOGIC_UNSIGNED library.

A straightforward code would use NUMERIC_STD library and define cnt as unsigned type.

 

[permute]

The line probably comes from a copy/paste. It is common in designs that stick to pure numeric_std. Basically, when IEEE defined how math should be done in VHDL, they decided that "+" would only apply to types that explicitly represent a number. Other decisions meant that types representing numbers would need to be recast to vector types. Synopsys previously created a std_logic_arith, and std_logic_unsigned package that could be used to get behavior similar to Verilog -- where vectors of bits are treated as unsigned values and have a "+" operation. However, other vendors also created their own libraries leading to compatibility issues that the numeric_std library was to resolve. Today, the synopsys and ieee libraries are both well supported for FPGAs.

I've always felt the decision to restrict "+" to only declared numeric types was a mistake*. It leads to the line of code you have here -- because "cnt" is used as a std_logic_vector the code would either need to declare "cnt" as an unsigned and then cast it to a std_logic_vector every time it is used, or would declare it as a slv and do the cast-add-recast seen here. The latter case restricts the micromanagement of types to a single line.

* it doesn't add any benefits to code readability. It adds another distraction to the developer. For anyone who declares cnt as an unsigned, it also removes warnings when unequal length vectors are compared ("01" = "00001" for an unsigned comparison as 1 = 1). (using std_logic_unsigned.all will also redefine "=" for slv to have this meaning).

 

[TrickyDicky]

But that would remove the explicitness from a stronly typed language.

For the benefit of those that insist on using std_logic_vector for arithmatic, numeric_std_unsigned and numeric_std_signed were added in VHDL2008, and they are an IEEE standard (they work the same as std_logic_unsigned/signed, but had all the extra textio support)