data pass between two clock domains

[anoop12]

Hi,

A design with two clock domains, domain1 and domain2.
1. Scenario1: domain1 is faster than domain2
2. Scenario2: domain2 is faster than domain1.

I have to pass 16 bit data from domain1 to domain 2 (status update).
How do I ensure that I capture correct data in domain2 ?

Thanks in advance.

 

[imbichie]

Hi Anoop,

Both case you can use a FIFO and read it out....

You can use the Status of Fifo for write and read out data ....

 

[xtcx]

I have to pass 16 bit data from domain1 to domain 2 (status update).
How do I ensure that I capture correct data in domain2 ?

Thanks in advance.

Well, there are few techniques which you can use. I consider ur clocks are not synch
1) Asynch FIFO
2) DP RAM
3) Double Synchronizer

Asynch FIFO is better for data\payloads not good for status\registers because it takes more resources.

DP RAM can be used but again not ok for status\registers. Also you need to implement ping-pong logic.

Double-synchronizer(3 DFF)

Case 1: Domain 1 is faster
Here can you mention your clock rate wrt domain2?. It has some hint. Lets say if you use 100MHz for domain1 and you want to transfer to 20 MHz domain which is about 5 times slower. First you should set a data_valid or a flag and hold it's high time more than 5 100MHz clk time and then clear it. This we call as wait state.
On the other side, use double synchroniser logic to read this flag under 20MHz clock, upon assertion read the 16-bit data. The CDC logic applies only for flag(data_valid) not for Data.

Case 2: Domain 2 is faster
Well, in this case, you do the same thing, but reduce the wait cycle to 1 instead of 5 as said in prev. case. No double-synchronizer is required, just a DFF pass through of valid flag is sufficient. Because a faster clock can capture the slower clocked registers data output with ease.

Hope it clears....