set_input_delay and set_output delay

[jaya sree]

hai every one,

In my project , set_input_delay and set_output delay values for input and output pins is reduced from previous release to present release. So will timing get better? I mean ,the less input and output delay values , the better for setup ? are constraints relaxed? is my analysis correct

 

[yadavvlsi]

Yes, It will improve in2Reg and reg2out timing. It will have no impact on reg2reg paths.

 

[jeevan.life]

Yes, It will improve in2Reg and reg2out timing. It will have no impact on reg2reg paths.

Hi Yadav

Can you please elaborate the answere. If set_output_delay is reduced, how the timing can get better. The path has to function faster inorder to meet the timing, so the constraints are tightened right?

 

[yadavvlsi]

Jeevan, output delay value is subtracted from clock period and you have yo meet reg2out path in remaining time. If output delay is less, you get more time to meet reg2out path. Same thing is applicable for in2reg also.

 

[childs]

What about hold time? I am guessing lower SID & SOD (set_input/output_delay) without -min or -max option will have negative impact on in2reg n reg2out hold time, but I am not sure the amplitude of impact.

A little add-on for the elaboration: SOD indicates the delay needed from the output port to the "imaginary" endpoint reg (which is outside your design). Reducing SOD means the delay from port to endpoint reg is now shorter; thus setup timing can get better. Same thing is applicable for in2reg also. (I stole your last line, sorry yadavvlsi)

 

[yadavvlsi]

Its ok dude. :smile: Hold is independent of frequency, hence time period. Reducing input delay and output delay will not have any effect on hold.

 

[childs]

Don't really agree that hold is not affected.
It's true that having smaller clock period does not affect hold; but what about smaller delay? Hold violation happens when data reaches the endpoint too fast (so fast that previous data was not properly consumed by the endpoint.) When we assume very small SOD, we are assuming the data delay from the output port to the destination outside only consume little delay (Agree until this point?). Won't the total delay be so small that hold time requirement is violated?

 

[chris_li]

Don't really agree that hold is not affected.
It's true that having smaller clock period does not affect hold; but what about smaller delay? Hold violation happens when data reaches the endpoint too fast (so fast that previous data was not properly consumed by the endpoint.) When we assume very small SOD, we are assuming the data delay from the output port to the destination outside only consume little delay (Agree until this point?). Won't the total delay be so small that hold time requirement is violated?

Childs, yes, in this case, buffer should be inserted to fix the violation like "removal" issue of reset path(in2reg).