Help! intel 4004CPU's register schematic

[Sheldon]

Here is a part of the schematic of intel 4004CPU, which is the address register. I analysed the circuit, it has a data_read enable, data_write enable, and a decoded address line A and B(not know how they are clocked). But I can not fully understand how the register works. It seems that the data is stored at paracitic cap at node C, but there is no charging path to this node. In that case, then a question is raised: is it a DDR or static RAM? Hopefully someone can understand this circuit and explain how it works.
Thanks!
I also attached the full schematic in pdf and bmp, which originates from Intel 4004 — 35th Anniversary Project. this reg is drawn in the pdf schematic page 1, which is easier to understand due to the notes on it.
View attachment i4004-schematic_reg_.bmp

 

[Sheldon]

I've found a wonderful tool for 4004 simulation, https://www.4004.com/2009/i400x_analyzer20091114.zip.
I can see the data in the reg is stored in the paracitic cap, and the data is periodically updated, which is more or less like a DDR. But I am still not sure whether it is really periodically updated or it is the program execution that makes this happen, anyway, with such a nice tool, it is not difficult to find it out.