static timing analysis

[ravipandu46338@gmail.com]

Hi.....,

Why postive skew is best for setup?
Why negtive skew is best for hold?

Can anyone help me please...,

 

[yadavvlsi]

Setup time is the minimum amount of time data must be stable before arriving active edge of clock. If skew is positive clock edge arrives late. So it is helps in meeting setup time requirement.
Hold time is the minimum amount of time data must be stable after arriving active edge of clock. If skew is negative clock edge reaches early. So it helps in meeting hold time requirements.

Setup time equation
Tcq + Tcomb<Tskew +T - Tsetup
Hold time equation
Tcq + Tcomb> Tskew + Thold

Check these links to understand setup and hold time calculation.
Setup time, Hold time
Only-VLSI: Setup and Hold TIme
Setup and Hold Time Calculations

 

[gourav.panda]

Hello Mr Yadav,
In the setup time equation we have got the clock period T but in hold time there is not Clock period T. why is it like this.?
i referred to the following link
http://asic.co.in/ppt/setup_hold_time.htm

And why is it said that hold violations are more dangerous than setup violations?

 

[santhosh.vlsi]

Hi read the timing closure chapter from the book "VLSI Physical Design from graph partitioning to timing closure" it may help you.....

 

[yadavvlsi]

Data is launched at one edge and it is captured at next edge. So setup is checked at next edge. Higher the frequency, time between two edges will be lesser and it will effect setup. Hold is checked at same edge because data launched should not be corrupted before it is captured. If there are setup violations, design can still run at a bit lower frequency but if there are hold violations, you can't run it at few Hz also.

 

[chakra]

also check local and useful skew concepts, know how and where you are going to apply these to time your paths better.

 

[gourav.panda]

hello yadav,
In your previous post you had written the equation of hold time

Tcq + Tcomb> Tskew + Thold
but in the explanation above it is stated that "Hold is checked at same edge because data launched should not be corrupted before it is captured"
so in that case why is the Tcomb in the equation present? if it is for the same clock edge and same flop then it should not involve the combinational delay before reaching another flip flop..

can u please relate your formula and explanation.

 

[yadavvlsi]

Data launched (by launch flop) should not be corrupted before it is correctly captured (by capture flop). So Combinational delay between two flops comes into picture.