flop with sync & Async reset

[V]

Hi

I came across a flop in one of the design in which the flop has sync and Async reset.

In real it should not b a problem, but is this kind of practice is preferred in RTL design?

kindly share your views. Thanks.

V.

 

[sam33r]

It depends on the design. As per the requirements we select the reset. But AFAIK designing of FSM's in an RTL code is usually done with asynchronous reset. This is because asynchronous reset takes less logic to implement, hence is faster and consumes less power.

 

[shitansh]

It depends on the design. As per the requirements we select the reset. But AFAIK designing of FSM's in an RTL code is usually done with asynchronous reset. This is because asynchronous reset takes less logic to implement, hence is faster and consumes less power.

Normally at top level, reset comes asynchronously, so first synchronizing reset is good practice, then in design synchronized reset goes to Asynchronous pin of all FF. That way Design will use optimal resources and there will not be any metastability issue.

HTH,
Shitansh Vaghela

 

[sam33r]

Normally at top level, reset comes asynchronously, so first synchronizing reset is good practice, then in design synchronized reset goes to Asynchronous pin of all FF. That way Design will use optimal resources and there will not be any metastability issue.

HTH,
Shitansh Vaghela

Sorry I didn't get it exactly what you are tying to say. Can you please elucidate? How do we combine both? Also I think the there is equal probability of a f/f being meta-stable for both async and sync reset. Please correct me if I am wrong.

 

[shitansh]

Sorry I didn't get it exactly what you are tying to say. Can you please elucidate? How do we combine both? Also I think the there is equal probability of a f/f being meta-stable for both async and sync reset. Please correct me if I am wrong.

For usage try refer below code.

Coming to next question, in ff metastability occurs due to two reason,
1) if your data input is not satisfying setup or hold requirement of ff
2) if your asynchronous reset is not satisfying recovery or removal time of ff.

So if you are using synchronized reset then 2nd problem will be fixed.

module top
(
   input  wire         clk
  ,input  wire         async_rst_n
  ,input  wire         in
  ,output wire         out
);
  
  wire         sync_rst_n;
  
  // reset synchronizer
  resetsync i0
    (
      .iClk        (clk         ),
      .async_rst_n (async_rst_n ),
      .sync_rst_n  (sync_rst_n  )
    );
  
  // dut uses sync_rst_n asyncrounousely
  dut i1
    (
      .clk   (clk       ),
      .rst_n (sync_rst_n),
      .d_in  (in        ),
      .d_out (out       )
    );    
endmodule 


module resetsync
(
   input  wire         iClk
  ,input  wire         async_rst_n
  ,output reg          sync_rst_n
);

  reg          rst_n_meta;
  
  always @ (posedge iClk or negedge async_rst_n)
    begin
      if (~async_rst_n)
        begin
          rst_n_meta <= {1'b0};
          sync_rst_n <= {1'b0};
        end
      else
        begin
          rst_n_meta <= 1'b1;
          sync_rst_n <= rst_n_meta;
        end
    end
endmodule 



module dut
(
   input  wire         clk
  ,input  wire         rst_n // asynchronous  active low reset 
  ,input  wire         d_in
  ,output reg          d_out
);

  // d-ff with asynchronous rest
  always @ (posedge clk or negedge rst_n)
    begin
      if (~rst_n)
        d_out <= 1'b0;
      else
        d_out <= d_in;
    end
endmodule

HTH
--
Shitansh Vaghela

 

[rca]

Synchronous reset does not act on flop element via reset pin, but act on the D input to change the flop contain on the next clock edge. Then we could say a synchronous reset is just a data changed, no?

 

[sam33r]

@Sitansh Thanks you for clarifying. I have one more doubt. Suppose we are using active high async reset and its high right from the start. Hence w/o the dependence on the clock the circuit will reset to the initial conditions, while in sync reset the circuit will reset to initial conditions only after the first clock edge arrives. Will this be a disadvantage of some kind like formation of latches because of default conditions not being me or any other?

 

[lostinxlation]

@Sitansh Thanks you for clarifying. I have one more doubt. Suppose we are using active high async reset and its high right from the start. Hence w/o the dependence on the clock the circuit will reset to the initial conditions, while in sync reset the circuit will reset to initial conditions only after the first clock edge arrives. Will this be a disadvantage of some kind like formation of latches because of default conditions not being me or any other?

This is the very reason why we need asynchronously resettable flops.
Most of the chip have multiple levels of clock muxes, selecting PLL clock or xtal clk or whatever clocks, and those muxes are controlled by registers which are clocked.
If the state of this register depends on a running clock, you'll never know if you can get a stable clock after power on and the chip may not boot up properly.

Most of the flops in the chip not required to be with async reset, but some MUST be on async reset.

 

[sam33r]

Okay! Thank you for clarifying so IMO we use async reset to some must required f/f in the top level as Sitansh suggested so that we are able to boot up the chip properly. And we don't use it everywhere just because it has higher chances of getting into meta-stable state.

 

[shitansh]

I have one more doubt. Suppose we are using active high async reset and its high right from the start. Hence w/o the dependence on the clock the circuit will reset to the initial conditions, while in sync reset the circuit will reset to initial conditions only after the first clock edge arrives. Will this be a disadvantage of some kind like formation of latches because of default conditions not being me or any other?

For this, try to observe carefully reset synchronizer module in my previous reply.
If you observe carefully then you will come to know that every where I have used asynchronous reset only, such a way that assertion of reset will be asynchronously, and only de-assertion will be synchronously.

Because of this your reset state of FF will not be dependent on clock edge, only state out of reset is dependent on clock edge.

Suggestion: Please read care fully solution and try to analyze it most of your questions will be answered by it self.

HTH,
--
Shitansh Vaghela