Synthesizable VHDL code...

[shaiko]

Hello people,


Can the following VHDL code be synthesized?


"input <= (conv_integer(number) => '1', others => '0');"


notes:

1."input" is defined as an std_logic_vector(15 downto 0) signal.

2."number" is defined an integer signal with a range of 0 to 15 ("number" isn't a constant).

 

[TrickyDicky]

It should be. It is just 16 sets of comparitors and muxes.

 

[shaiko]

Yes...that's what I thought.
However, Modelsim shows the following warning:

"Non-locally static choice (association #1, choice #1) is allowed only if it is the only choice of the only association".

It's not an error - only a warning...
Modelsim never fails to show the "smartest of phrases" when it doesn't agree with your code.
I wish, it wasn't so "smart" and speak plain english...

 

[TrickyDicky]

Its not a synthesisability question, its a VHDL rule question.

Instead I would stick your code in a process like this (this breaks no rules):

process(number)
begin
  input <= (others => '0');
  input( conv_integer(number) ) <= '1';
end process;

 

[shaiko]

I don't think that it would yield the same result.
If "input" is defined as a signal, the 3rd line of your code will be ignored (input <= (others => '0') becase it's overwritten in the next line.

 

[TrickyDicky]

It is identical, but legal VHDL code.
Everything is assigned a '0', but only 1 bit is overwritten with a '1'.

 

[shaiko]

No, the assignment of zero's will be ignored!
Signals are assigned when the process is exited...so the first statement won't be executed. Only the second one.

---------- Post added at 15:56 ---------- Previous post was at 15:55 ----------

No, the assignment of zero's will be ignored!
Signals are assigned when the process is exited...so the first statement won't be executed. Only the second one.

 

[TrickyDicky]

Try it - you'll see everything gets assigned to '0', and then the selected bit is set to '1'. Only 1 bit is overwritten, not the entire signal, so everything else remains at '0'.

I have just tried it myself in modelsim to prove I wasnt being an idiot.

 

[FvM]

No, the assignment of zero's will be ignored!
Signals are assigned when the process is exited...so the first statement won't be executed. Only the second one.

It's no that fruitful to decide about working of VHDL code based on pure assumptions. You should understand how things works. Vector signal assignments are bitwise, so the second one only affects the selected bit and leaves the others unchanged.

 

[shaiko]

You're right!
It works fine and a decoder is inffered.
Thanks

---------- Post added at 17:58 ---------- Previous post was at 17:00 ----------

BTW:

Can you consider a "decoder" as a private case of a "mux"? (a mux with constant inputs)

 

[TrickyDicky]

In this case you have 16 muxes each with constant inputs.

 

[shaiko]

Quartus shows them as Decoders...this is the reason I asked

 

[FvM]

At the end (in the gate level schematic), every bit of signal "input" will be driven by a LE with 4 inputs, representing the "number" signal, at least for the implementations you have shown. It shouldn't matter which behavioral oder other description is used to define it.