what are the cts main goals?

[ee1]

can anyone list the cts main goals?

and another question:
when is the best stage during the asic flow to check timing in sta tool? after route?

thanks!

 

[ckshivaram]

The goal of CTS is to minimize skew and insertion delay

check this
Azuro: PowerCentric - Clock Tree Synthesis
Physical Design
ASIC-SoC-VLSI Design: Clock Tree Synthesis (CTS)

---------- Post added at 20:01 ---------- Previous post was at 19:58 ----------

this one for your second question
http://www.newbiers.com/soft/UploadFile/digital_design/20100823/paper9_1.pdf

 

[AdvaRes]

The goal is to have a clock balanced circuit with a tolerable skew in the clock tree leafs.