Any job openings for freshers in VLSI?

[suhassmiley]

Please let me know if there are any job openings for VLSI freshers at any place bangalore, chennai, noida or pune.

 

[ckshivaram]

No........... VLSI freshers has too less oppurtunity as of now......

 

[ckshivaram]

RTL coding (Verilog or VHDL)
Synthesis
Floorplanning/PowerPlanning
Placement
Clock routing
Routing
Physical Verification(LVS/DRC)

RTL Coding+ Synthesis ------> Front End
Synthesis+ Floorplanning to Physical Verification -------- Backend

Synthesis can be a part of front end or Backend which can be carried out by either frontend engineer or Backend engineer.

RTL coding engineer called frontend engineer
Reminaing steps who carry out called Physical design Engineer or Backend Engineer.

In short , The Front End starts in the RTL design (VHDL or Verilog), and includes Functional Verification (Simulation, Formal Verification, etc), and in some cases Logical Synthesis which can also be a part of the Back End flow!

---------- Post added at 11:13 ---------- Previous post was at 11:12 ----------

the tools used are
• Simulators: VCS, VCS-MX, IUS (NC), ModelSim
• Synthesis: RTL Compiler (RC), Exemplar Leonardo
• Coverage: VCS Coverage Metrics

Equivalence Checking:
• STA CeltIC
• FPGA Xilinx, Altera and Actel

---------- Post added at 11:14 ---------- Previous post was at 11:13 ----------

In today ASIC industry the design is portioned into front end and back end as explained below.
Front end:
Enter the design in one standard format (which EDA tools can understand)
Analyzing the requirements and high level design (identifying various blocks in design)
RTL design evolving the necessary micro architecture for the each block
VHDL, Verilog, other HDLs, Netlist etc.
Developing necessary techbenches for functional verification.
Simulation and model verification using standard simulators
Integration of all the blocks and top level simulation.

Back end:
Synthesizing the design, fixing any bugs (if any part of code is not synthesizable)
Floor planning as the targeted silicon area
Invoking the ASIC back end tools (Mapping extracted Netlist cells to technology specific cells)
Place and root as per the required timing and clock constraints
Extraction of models from synthesis outputs
Timing simulation and functional verification
Sending the design to the FAB and getting the chip manufactured.

 

[sanju_]

thanks again
ASIC is different then FPGA'S
does FPGA have same scope as ASIC.
even i am fresher thats the reason asking

 

[ckshivaram]

when you design an asic chip, lot of FPGA is used in its development...

there is not much difference between the two, as fpga is a kind of programmable asic.
FPGAs are good for prototyping and limited production.cIf you are going to make 100-200 boards it isn't worth to make an ASIC

However, if you are going for volumes and competitive pricing you have to go ASIC.

FPGA have a lot of built-in features to take advantage of, such as memories and highspeed I/O, embedded CPU..
FPGA is not efficient in speed, area and power and it has special memory(dual port), multiplier and clock tree. So, after prototyping, you need to change them.

but both have equal scope in the industry, but ASIC have a upper hand....

 

[ckshivaram]

at what level you require the documents??? begineers or intermediate or at design level....

and what specific documents you need?

---------- Post added at 12:05 ---------- Previous post was at 12:04 ----------

your requirement is different from the thread topic.... you are intruding into others thread...........

 

[suhassmiley]

am on the verification part.. I have done my internship building the verification environment for the AXI4 protocol.. so m mainly looking for the frontend verification using System Verilog or OVM or VMM... if u know any openings please let me know sir..

 

[ckshivaram]

ok will let you know in the group announcement of the board if any news are there........