I have some couple of questions on design planing plz any one ans to these questions?

[jeevan.akula]

I have few questions on physical design plz any one ans to these questions?

Hi,
I am new to physical design .. i have some questions here plz any one ans to these questions..?

1) How we will decide aspect ratio, with an example?
2) How to calculate core area?
3) How periphery area is decided ...?
4) Is that key board margin should equal on the four sides of core area?
5) To set up the data what are input and outputs ?
6) Is def only the file as input to CTS stage? what is the output file? As well as for routing and chip finishing stage?
7) Why we are using SPICES instead of verilog netlist for LVS check?
8) what it exactly specifies align bus signal pins b/w macros ?
9) What are the power network constraints? How it helps to reduce the IR drop analysis ?
10) What are black boxes ?

Thanks in advance .....
Regards,
Jeevan

 

[BradtheRad]

All I can help with is #10.

Black box is a buzzword for a step in a procedure where the main idea is that the job gets done. Details of how it's done are either (a) unknown, (b) unimportant, or (c) can wait til a later time.

Someone may handle the details. In other words to build the black box. He may not want to reveal the details. He simply says 'I made a black box to do that.'

 

[phoenixpavan]

Hi Jeevan,

1. Aspect ratio in most cases we try to make it 1...
2. Core area is calculated based on no of instances, utilization factor
3. Periphery area = core area + pads..so you need pad information also
4. I suppose its keepout margin..its not necessary to have same value..depends on pin locations
5. u need logical/physical libs, tech file, tlu+, netlist, constraints..
6. DEF is a format to exchange information between various stages of PnR/ between different tools..u can use a DEF file or the CEL saved in MW from previous stage..
7. Spice is the electrical characterization of the layout...since LVS checks for things like open,shorts etc u need electrical characteristics to match between Layout and schematic...verilog is simply connectivity information
8. If pins of macros are not aligned properly it takes more routing resources and creates congestion...so we try to keep communicating pins nearer
9. PN constraints define the width, spacing,layers,ring size and other aspects of power straps...so if IR drop is unacceptable changing these values will help in reducing IR drop
10. Black boxes are any blocks for which we have only interface information...we do not know the functionality of the block and internal connections....at PnR level we have to make use of the ETM for timing analysis in case of black boxes....this is mostly the case for IPs we may want to use in our design.

useful??

cheers

 

[jeevan.akula]

Hi pavan,


your ans are simple and good .... thank u so much