Timing: What causes setup and hold requirements

[jagz]

Hi, I have a very basic question. I m sure this would have gone through most of the people's mind.
All knows what are set up and hold time and what all would happen when they are violated. But, when we consider a master slave latch, (i.e constructing blocks of a flip flop) , where is the actual requirement of the set up and hold time required? Imagine two latches connected in the form of mater n slave, the second one having inverted clock compared to the first, where and how the set up and hold time are considered. It would be great if some one could explain this with respect to master slave latch.

 

[lostinxlation]

If a master latch doesn't have data, a slave latch doesn't get that data, so the setup and hold are the property of a master latch. Of course, a slave latch has its own setup and hold time, but apparently meeing that requirement is responsibility of cell designers, not people using the cells.

 

[chipmonkey]

jagz,

The setup and hold time are caused by the gates present in the master latch. Remember the latches that constitute the master-slave are level sensitive than edge sensitive. so as long as the clock is high, it latches the input. the data presented at input of master takes some time to reach the output of master, ie the input of slave. It is this time that constitutes setup time. If the data at master input changes at a time later than the setup time then this data cannot reach the salve input by the time the slave gets active and the slave latches the old data at the slave input.

now consider the data changing exactly or just after the posedge of slave clock. The master will still latch this data since the clock inversion at master will take place only after the propagation delay of the inverter. Hence this data will be captured by master and subsequently by slave causing data over write. Hence the hold time requirement.

Generally the setup time is approx equal to prop delay of 3 gates and hold time approx equal to prop delay of 1 gate.

 

[lijo911]

I think setup thing is related to master and hold is related to slave latch......
because before the clock edge the master latches data into it.......and data has to be stable "setup" time before clock edge. setup time in other words is the time required to charge/discharge the input capacitance to a proper logic level.....When clock edge happens, the data latched by master is available at the input of slave latch....but clock to slave didnt arrive (because of inverter in the clock path).......so data reaching the input of slave latch has to be stable till the inverted clock for the slave latch arrives.....this is the hold requirement....:smile:

 

[lostinxlation]

When clock edge happens, the data latched by master is available at the input of slave latch....but clock to slave didnt arrive (because of inverter in the clock path).......so data reaching the input of slave latch has to be stable till the inverted clock for the slave latch arrives.....this is the hold requirement....:smile:

It doesn't matter if slave input is stable or not when the clock rises. Once a wrong data, regardless of by setup or hold violation, is captured by a master latch, it propagates to a slave latch while a slave latch stays on in the same cycle period, and the flop outputs the wrong data.

Basically, when a master latch gets a wrong data by a setup or hold violation, the game is over.

 

[lijo911]

Wat happens if the master is triggered by a clock and slave by the same clock after passing thro an inverter??..........master is off as soon as the clock goes low........is hold violation possible there??.........because slave is getting triggered later compared to master.........

 

[lostinxlation]

Wat happens if the master is triggered by a clock and slave by the same clock after passing thro an inverter??..........master is off as soon as the clock goes low........is hold violation possible there??.........because slave is getting triggered later compared to master.........

If both of a master and slave latch are on at the same time,you have a hold violation at the slave input.
there is always a setup/hold requirement for any sequential cells regardless of that it is a master latch or a slave latch, but master to slave in a flop is not something you can do anything about, if you are just using the standard cells. That must be taken care by a cell designer.

 

[vani123]

Hi Jagz,

I was googling about setup and hold requirement then come to know about a interesting blog- may be it wil lhelp you.

h**p://vlsi-expert.blogspot.com/2011/04/static-timing-analysis-sta-basic-part3a.html

-Vani

 

[lijo911]

if i am the cell designer and i am plannin to design the standard latches.......then wat all things to take care??........ and in between the latches doesnt ve setup and hold times.....they ve recovery and removal times i guess...........