numeric_std (signed/unsigned) vs std_logic_1164 (std_logic_vector)

[nabla101]

Hi, I don't understand what is the benefit of using unsigned or signed types from IEEE.numeric_std library over std_logic_vector from IEEE.std_logic_ 1164, since you cannot assign integer values to either of these types, but still have to define individual elements of an array. For example:

variable u_int : unsigned(3 to 0) := "0000";

is legal, while:

variable u_int : unsigned(3 to 0) := 0;

is illegal. I thought the whole point of these types was to allow you to c onvert from std_logic_vector, easily perform arithmetic on them as integers, and then convert back to std_logic_vector...wouldn't it be better if the compiler determined the upper and lower values the signed or unsigned integrs could have based on the natural range they are given, then allow you to make straight-foward integer assignments (such as in the second case above), and then determine if the integer you try to assign is in range or not, instead of complaining that it is not in the format "xxxx".

 

[vipinlal]

Read this:
VHDL coding tips and tricks: Why the library "numeric_std" is preferred over "std_logic_arith" and others?

 

[TrickyDicky]

if you want something to be an integer, then use an integer. if you want to access the individual bits, then use an unsigned/signed

The problem with std_logic_vector is there is nothing to say whether it is signed or unsigned. You cannot do signed and unsigned arithmatic in the same file when you use std_logic_vectors, whereas numeric_std does.

you cannot assign an integer to an unsigned, because it and unsigned is not an integer (remember vHDL has strong typing). But you can do anything else with integers:

signal some_unsigned : unsigned(7 downto 0) := to_unsigned(143, 8);

some examples of unsigned and integers:

if some_unsigned = 77 then
some_unsigned <= some_unsigned + 1;

etc etc.

There is nothing that forces you to ever use std_logic_vector. Why no keep unsigned and integers in your ports?

 

[nabla101]

Thanks, I understand what you and that article are saying, but I still have questions.

I read somewhere that it is not a good idea to use signed, unsigned or integer types for ports, since sy thesis tools will always resolve them to std_logic_vector anyway, and this may result in some kind of problems. Can you comment on this?

Also, what is the difference between doing a conversion:

signal some_unsigned : unsigned(7 downto 0) := unsigned(143);

and

signal some_unsigned : unsigned(7 downto 0) := to_unsigned(143);

and which is better to use and why?

Finally, if you can do this conversion:

signal my_slv : std_logic_vector(7 downto 0) := std_logic_vector(some_unsigned);

then is there a conversion defined:

signal my_slv : std_logic_vector(7 downto 0) := to_std_logic_vector(some_unsigned);

..analogous to to_unsigned() above? And again if so, what is the difference?

 

[TrickyDicky]

Thanks, I understand what you and that article are saying, but I still have questions.

I read somewhere that it is not a good idea to use signed, unsigned or integer types for ports, since sy thesis tools will always resolve them to std_logic_vector anyway, and this may result in some kind of problems. Can you comment on this?

At the end of the day its all bits. But in the code theres nothing wrong with using std_logic_vector, unsigned, integer, boolean, my_special_amazing_type or any other thing in a port map that can be represented ultimatly with 0s and 1s (this includes enumerated types you might normally use in a state machine). Its normally best to keep to a vector type (std_logic_vector, unsigned, signed etc) at the top level so you can map each bit to a specific pin, but otherwise, fill your boots with whatever types you want.

What is the difference between doing a conversion:

signal some_unsigned : unsigned(7 downto 0) := unsigned(143);
and

signal some_unsigned : unsigned(7 downto 0) := to_unsigned(143);

A big difference, because the first one is not valid VHDL (which I will explain in a minute), and the second one needs another argument to say how many bits you want.

Finally, if you can do this conversion:

signal my_slv : std_logic_vector(7 downto 0) := std_logic_vector(some_unsigned);

then is there a conversion defined:

signal my_slv : std_logic_vector(7 downto 0) := to_std_logic_vector(some_unsigned);

..analogous to to_unsigned() above? And again if so, what is the difference?

The second one doesnt exist because its not needed. In VHDL you can type convert between similar types. std_logic_vector and unsigned/signed are arrays of std_logic:

type std_logic_vector is array(natural range <>) of std_logic;
type unsigned is array(natural range <>) of std_logic;

so as they are basically the same, you can just type convert:
some_slv <= std_logic_vector(some_unsigned);

integer is not an array of std_logic, and so is not a similar type to unsigned/slv, so you need a conversion function, hence:

some_unsigned <= to_unsigned(some_integer, some_unsigned'length);

Does this help explain things?

---------- Post added at 00:44 ---------- Previous post was at 00:42 ----------

Just to add to my first point - theres this lingering idea that you must have std_logic_vector in ports, because in the old days it was the only type accepted by synthesisors for ports. But for at least the last 5 years, thats not been the case.

 

[nabla101]

Very helpful indeed, thanks. I have one more question. If I use alot of integers in my code, but the integers are only representing small values in general, will the synthesis tools optimise out any redundant bits (i.e. more significant bits) to prevent each integer signal/variable or hardware construct being synthesised as 32-bit, which could fill up a chip?

 

[vipinlal]

Dont worry. The synthesiser will optimize the code for you. For example in xilinx ise, it will discard the unused bits of integer. Read this post for more:
VHDL coding tips and tricks: Synthesis warning : Node of sequential type is unconnected in block

I think most decent synthesisers will do the same.

 

[TrickyDicky]

Its usually best to restrict it. For example, the synthesisor cannot check the min and max values on a counter. Optimisation can only occur if it only connects to a fixed sized memory or similar.

If you just used it to check a value for other logic, it would make it 32bit.

This is the only worry with integers, you have to get a bit careful about this, but its not much of a problem.

 

[nabla101]

Thanks both. If unsigned, signed, and std_logic_vector are all arrays of std_logic, then what exactly is the integer type? Its not a 32 element (bit) array of std_logic?

 

[TrickyDicky]

The integer type is just the integer type. It is a base type you can use without using the package ieee.std_logic_1164.all; In VHDL integers exist in the std.standard library, which is included by default in all files, and is defined as:

type integer is range -2^31 to +2^31-1; (this range can be set by the simulator/synthesisor, it is not restricted to 32 bits, but everyone uses 32 bits).

Std_logic was introduced to give people access to individual bits. You also have to remember that std_logic is not just '0' or '1', it can be 7 other things aswell ('U', 'X', 'H', 'L', 'W', 'Z' and '-'). This states cant be acheived with the integer type.

 

[FvM]

The integer type is just the integer type.

Yes. How is it synthesized would be different question. Depending on the range, the synthesis tool uses either UNSIGNED or SIGNED to represent the integer type.