Predictive Technology Model (PTM) and process corners

[Janna13]

Hi

I need to use PTM model PTM - Latest models but I need also to check the behavior of low power transistors under process variations (FS, SF, TT, SS and FF).

Do you know how can I do that?

Thanks you for your help

 

[erikl]

On the PTM home page, instead of Latest Models go to Nano-CMOS, put in your technology parameters (default ones, or those you can get from Latest Models), then click Submit, and you can get (level 54) model parameter files at least for TT, SS and FF process variations.

 

[Janna13]

Hi

Thank you for your help, now it looks much better
I still have some questions, hope you can help with this.
1. What is level 54? I also see it in the *pm files.
2. If I need SF corner, does it make sense to take params for nmos from SS corner and for pmos from FF corner and
combine to new *pm file?
3. The "nano cmos" is only for bulk cmos, while I need it for low power cmos. Since I see the percentage of change in
params between SS, FF and TT; does it make sense to apply the same percentage of change to params but in LP and
this way build the LP model with process corners?

Thank you again for your help

 

[erikl]

1. What is level 54? I also see it in the *pm files.

BSIM4 model files.

2. If I need SF corner, does it make sense to take params for nmos from SS corner and for pmos from FF corner and combine to new *pm file?

Sure!

3. The "nano cmos" is only for bulk cmos, while I need it for low power cmos. Since I see the percentage of change in params between SS, FF and TT; does it make sense to apply the same percentage of change to params but in LP and this way build the LP model with process corners?

Yes, of course. But you should be aware that the percentaged deviation depends on the process, and on the sigma value which is used for the percentage, and this in turn depends on how many sigmas away from the TT values your foundry will test and deliver.

 

[Janna13]

Thanks again.
1. Since I need to find corners for predictive model and for now I don't really know the foundry
or the process, do you have a better idea, how to find corners for LP?
2. I would like to check it also for lower then 32nm (this is the lowest in Nano CMOS), do you
think I can still use the same percentage of 32nm process but to apply it to 22nm and 16nm?

Again thanks a lot for your help, maybe I'll even understand it soon

 

[erikl]

... for now I don't really know the foundry or the process, do you have a better idea, how to find corners for LP?

No, actually not. As long as you have no info about process and foundry, just use these percentaged values; they present good "mean values" for the speed deviations.

Don't forget to add voltage and temperature changes for your best/worst case analyses.

---------- Post added at 22:06 ---------- Previous post was at 22:00 ----------

2. I would like to check it also for lower then 32nm (this is the lowest in Nano CMOS), do you
think I can still use the same percentage of 32nm process but to apply it to 22nm and 16nm?

Most people say the speed deviations (for the same sigma) grow at lower process sizes, but unfortunately I can't give you any values :-(

May be this article on statistical variation is worth to be read.

 

[Janna13]

Thanks :smile:

 

[dhaval4987]

Don't forget to add voltage and temperature changes for your best/worst case analyses.
QUOTE]

Hello. I have a small question. Can we add Temperature info inside the model file?

Also,

I am using 45nm PTM models.
I have to make many different models with for CMOS with different operating condition. Starting from SS to FF. And I have to vary Vdd, Vthn, Vthp and Temperature for my analysis.

How should I vary these? Is Vdd most dominant? Does temperature have more effect then Vthn and Vthp?

What I thought was- I will Keep Vdd nominal, Temp nominal and generate TT, FF, SS, SF and FS. (5 models)
Then will vary Temp above and below nominal Vdd and generate TT, FF etc in each case. (5+5=10 models)

Same process I will repeat by lowering Vdd and increasing Vdd. (15+15)
and in the end- extreme conditions.
Is this the correct way?

 

[erikl]

You could either use a parametrized "main model" and change the parameters via appropriately called library sections like in this GPDK file (clipping) : View attachment corner-section-example.txt , or you can put together more specialized corner sections e.g. for various devices with varying corner behaviour: View attachment gpdk.txt .

 

[dhaval4987]

I understand and appreciate your response. But the question was- how to determine the value of Vths, Vdd and Temp variations? And which is the order of dominance? I believe Vdd is the most dominant. But not sure about others.

 

[erikl]

... the question was- how to determine the value of Vths, Vdd and Temp variations? And which is the order of dominance? I believe Vdd is the most dominant. But not sure about others.

Vth, Vdd and Temp variations usually are covered by the models itself, this is standard with Spice-like analyses. Vth variation (with current, voltage, temp) is inherently contained in the MOS (and other devices') models; Vdd and Temp are given fixed or swept in the simulation bench, the Spice analysis calculates their effects via the parameters given in the models.

If you like, you can also determine (fix) Vdd and Temp values in the respective sections (s. my former contribution).

Re. order of dominance: this clearly depends on the mathematical dependency (log, sub-linear, linear, over-linear, exponential) between cause & effect. Temp often affects parameter behavior exponentially, so in many cases is dominant. But of course this also depends on the variation range of the causing parameters.

HTH!

 

[dhaval4987]

YTH!

I ll try today. This made it more clear what I wanted to do. I will use Vth variation at given Vdd and Temp.

Thanks

 

[Oveis.Gharan]

Dear all,
I read your questions and answers.
They are so helpful.
But finally i could not underestand how many percent in a technology should be assumed as variation range. On the other hand i want to know specificly how many variation in Thereshold Voltage in 45nm CMOS Technology is seen. (How many percent).

Dear dhaval4987 , Did you find out the amount of variation in 45nm Technology Node?
Thnks in advance.
Oveis

---------- Post added at 11:20 ---------- Previous post was at 11:18 ----------

Thanks again.
1. Since I need to find corners for predictive model and for now I don't really know the foundry
or the process, do you have a better idea, how to find corners for LP?
2. I would like to check it also for lower then 32nm (this is the lowest in Nano CMOS), do you
think I can still use the same percentage of 32nm process but to apply it to 22nm and 16nm?

Again thanks a lot for your help, maybe I'll even understand it soon

Dear Janna,
What is the difference between Bulk CMOS and Low Power CMOS?

Thanks in advance,
Oveis

 

[erikl]

What is the difference between Bulk CMOS and Low Power CMOS?

These are quite different categories: There are Bulk CMOS and SOI CMOS processes. With both process categories, beside their standard process flow you may have options: High Speed CMOS with lower V_th, and Low Power CMOS with higher V_th than in the standard process flow.

 

[Oveis.Gharan]

Thanks Erikl.

 

[dhaval4987]

Oveis,

The amount of variation is something you should try to seek from the industry. The professor with whom i was working got me some data from industry. dont know whether there is any other way to do so or not,. I am sure there must be a way out of it.

 

[Oveis.Gharan]

Oveis,

The amount of variation is something you should try to seek from the industry. The professor with whom i was working got me some data from industry. dont know whether there is any other way to do so or not,. I am sure there must be a way out of it.

Dear dhaval
How could i find such information from Industry?
Could you please share me the data which you have got frome your advisor?
It is so nessesary for me. Becaouse of some imposed constraints i think it could not gain these data from fabs.

Thanks in advance.
Oveis.

 

[erikl]

How could i find such information from Industry?
... Becaouse of some imposed constraints i think it could not gain these data from fabs.

Such info is always confidential; all foundries disclose it only to customers after them signing an NDA.

So if you can't get this info (because you aren't a semicon customer), why not use the published values from the PTM people, see my post #2 above. This info is published for educational purpose.

 

[Oveis.Gharan]

I dont know how many variation should be inserted for vth in PTM nano-CMOS page.
What do you suggest?

 

[erikl]

Use the default values -- if you don't know better -- they are quite meaningful for these processes.
And they cover 3σ (standard deviations), which means more than 99% of all dice.