200 pts - LNA design improvement

[_SquiD_]

lna design

Hi there,
I really need your help. Regarding the performance improvement of the following LNA (low noise amplifier):

**broken link removed**

!!! I need a full analysis of this amplifier, who presents the most detailed analysis will receive 200pts .
I used this amplifier in a chain that processed a signal. So I need it to be as low noise as possible and the PSRR as good as it could get. Firstly, any suggestions regarding the improvement of the PSRR ?
I will try to present some results from my simulations: I used gpdk technology. The transistor dimensions that I chose for this amp are:
M1 = 5.2u / 400n__________M2 = 5.2u / 400n_________M3 = 12u / 7.5u
M4 = 12u / 7.5u __________ M5 = 34u / 2u __________M6 = 26u / 2u
M7 = 34u / 2u __________ M8 = 12u / 1u__________ M9 = 12u / 1u
M10 = 6u / 2u __________ M11 = 1u / 1u

(*) So far I've obtained values of: PSRR+ = 25dB, PSRR- = 32dB.

**broken link removed** **broken link removed** **broken link removed**

(*) In the first pic it's presented the Vout of the amp in open-loop.
(*) As I said I need the LNA for processing a certain signal... at certain point in my circuit I filter the signal wave using a FTJ (and it looks okay) ... but after I repeat it using my amp ... the signal looks worst, it has some spikes all along the signal. How can I correct this problem ?!

(*) In the 2-rd figure: FTJ filter and LNA which should repeat my signal wave.
(*) In the 3-rd pic: the two signals obtained: 1- the one that was filtered , 2- after being repeated.

Thanks in advance,

- SQD -

 

[bigworm]

corner frequency mosfet cadence spectre

cascode current mirror will get you better psrr if there is headroom....

 

[_SquiD_]

nooise analysis of lna

I see everybody left on vacantion ... nobody wants to help ?!

 

[seej]

200 pts

At what frequency are you operating the amplifier ? What is your noise cutoff frequency ? Based on that the circuit can be optimized for flicker or thermal noise or balanced between the two. Let me know.

Also I am not sure why you are using the capacitor. The spikes seem to be short charge discharge cycle I would want to try and experiment with the capacitors and see if i get some effect.

 

[_SquiD_]

psrr lna

The amplifier it is beeing used let's say at a frequency of 100Hz.The capacitor is used for compensation. The schematic is from Allen and Holberg's book.

What do I have to plot to display the noise figure in Cadence?

- SQD -

 

[geex]

site:www.edaboard.com

I assume you can do a pnoise analysis to get a noise performance on ur circuit.

In the ADE ( Analog Design Environment ) do,

Analysis -> Choose -> pnoise

 

[seej]

design improvement

Ok at 100Hz it has to be flicker noise thats going to bother you. I think Holenberg gives you an expression for flicker noise of an OPAMP. Anyways the trick is that only the input MOSFETS and the MOSFETS in series with it that contribute to the noise not the biasing MOSFET M5 or output stage . So larger its dimensions lower you noise. Also another thing you can do is find the optimum biasing current to lower noise figure. While there are analytical solutions for this I suggest a simulation based solution. Another approach I think used in a lot of comercially available MOS OPAMPS is to make the corner frequency as low as 10 Hz. Since thermal noise is much less than flicker noise you end up achieving noise as low as 1 nV/ root hz. This without going for very large MOS dimensions.

Both Spectre and Spectre S have provisions for noise analysis..... just like the transient analysis you have done. You just have to choose the anlysis and select input and output refered ports.