2 statge OPA design problem

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andy2000a

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In p-input CMOS 2 stage OPA ..
for AC simulation , if Vcc=5v , we usuall use

v1 ip 0 2.5v ac 1
r1 in out 100meg
c1 in vss 100u

(from CMOS circuit design layout & sim )

1. but why use 2.5v ? just for keep input mos in active region ?
if Vcc = 3.3v vip=2.5 maybe cause p-input mos cutoff

2. why use AC 1 ?? can I use 0.5v or 0.1v for ac simulation
if I use vip ip 2.5v ac 0.5

3. hspice list have input device gm , gm_effect
waht is gm_effect
 

The source at 2.5V sets the input common mode to that voltage. Depending on your technology, you have to verify that this value is within the valid common mode range of your amplifer. Your supposition when Vcc=3.3V is correct.

You use AC 1 so that the output signal you get is the amplifier's gain. But you can use whichever value you want, provided that you scale the output result to obtain your gain.

Concerning your last question, veryfy with your simulator manual and model card used, what the meaning is of gm_effect(ive).
 

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