[SOLVED] 2 Stage Op-Amp Stability Analysis

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Shady Ahmed

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I designed a 2 stage op-amp, the schematic is as follows (i used a vcvs as the error op-amp for now):



as i wanted to check the stability,
* First i plotted the bode plots (both mag & phase of differential output of stage 2) (showing that the DC gain is 40 dB, GBW = 180 MHz & Phase margin = 56 degree)



* Second i inserted diffstbprove in the CMFB circuit to check its stability, so the updated schematic is as follows



and the stb analysis plots are: (which indicates that it is stable)






Now, i wanted to check the differential mode stability , so i created a test bench as follows



However, the output plots from the stb analysis is weird !! here it is :




So, my question is , is any of the tests i performed wrong? should i only use the gain & phase plots of the differential output as the first test ? or should i depend on the differential mode test using the diffstbprobe? and why is the result very weird?

Please help me with some hints about the stability analysis and which loops should be tested & how.
Thanks
 

Hi,

What Vout/Vin do you measure: where you apply your input signal and where do you measure output signal?

In feedback loops you're using only capacitors?
 

t4_v said:
where you apply your input signal and where do you measure output signal?
Click to expand...

The input signal is at the Voltage sources attached to the i/p transistors in the first stage and the output is the AC (vo_2_r - vo_2_l)


t4_v said:
In feedback loops you're using only capacitors?
Click to expand...

At the first test i am testing the open loop, so i just inserted Capacitive load.
In the second test, i am trying to test the op-amp as integrator, so i have Capacitor in the feedback and resistor before the op-amp i/p as the standard way of implementing an integrator.

Thanks for you concern

- - - Updated - - -

As for more details , i performed the test bench with sine wave and expecting a cosine wave as the output of the integrator which is clearly not the case.

The image shows the waveforms of:
Vinput_differential (sine wave with amplitude = 200mV )
Vin+ & Vin- are the input points of the op-amp.
Vout+ & Vout- of the op-amp


Clearly the output of the op-amp saturated to Vdd (1.2v) ,, that's a big problem of course ,,, so what is the cause? stability problem? The values of the R & C ? the CMFB circuit isn't working?


Shown in the next image, the DC operating points.
The output node voltage is at 633mV instead of 600mv (ideally), the 33mV difference maybe the problem? if yes, how can i fix it?

Help please.
Thanks
 

Hi,

Firstly, the schematic here: would be open loop if you put inductors instead of capacitors.

Secondly, please provide the test circuit for the results you pictured here: .

Thirdly, 33 mV difference is not a problem right now. Do not concentrate on this.
 

t4_v said:
Firstly, the schematic here: would be open loop if you put inductors instead of capacitors.
Click to expand...

I don't understand what you mean, why would i use inductors? I want to test the op-amp as integrator , so i used that schematic.

t4_v said:
Secondly, please provide the test circuit for the results you pictured here: .
Click to expand...


The following is the test bench setup , which is an integrator with the input signal as sine wave.
Attached the Output also, with the signal naming.


**broken link removed****broken link removed**

Apparently, the output signal saturates at Vdd (1.2) .

Thanks for your time
 

Sorry for inductors. I thought that you used this testbench: to plot AC vs frequency plot to measure phase margin.

Your attachments do not work.

I would like to see the testbench for these results: to help you in understanding why outputs saturate to power supply 1.2 V.
 

Sorry for that , i don't know why the attachments didn't work.






Attached , a new test bench with a new output graphs (More detailed with the nets name)
 

Ok, now it's clear.

First of all, any opamp must have a DC feedback loop (an exception is using an opamp as a comparator) if a feedback loop is used. Thus, in your case I would either put MOhms (mega) resistors in parallel to capacitors or reset capacitors through parallel switches.

Secondly, I cannot find any usage of fully differential amplifier as integrator for both inputs.

Thirdly, if DC operating point is ok as it is in this case, because you checked it and outputs are around VDD/2, then I would try to test the opamp using for example a testbench here https://www.linear.com/product/LTC1992 .
Your input signal will be 0V +/- 1.2 V and outputs should be 0.6 V +/- 0.6 V.
However, firstly I would not check rail-to-rail operation. Let's try for example 0V +/- 0.6 V as input signal and the outputs should be 0.6 V +/- 0.3 V.
 

I think the CMFB would be enough , it is considered as DC feedback, however i did add resistors as u suggested and nothing changed.

t4_v said:
Secondly, I cannot find any usage of fully differential amplifier as integrator for both inputs.
Click to expand...

I am designing a Sigma Delta ADC, which has integrators as a main component, and it is fully differential , so, that's what the integrator should look like.

t4_v said:
try to test the opamp using for example a testbench here
Click to expand...

Ok, i'll look into that testbench.

Thanks for you help.
 

Yes, sorry. I forgot about CMFB.

Ok, I see now. I saw an usage of fully differential opamps in delta-sigma circuits, but they were used in switched capacitors configurations.
 

t4_v said:
I saw a usage of fully differential opamps in delta-sigma circuits, but they were used in switched capacitors configurations.
Click to expand...

Yes, that's very much like it, but i am working on a Continuous time Sigma Delta, so , that should be my integrator. However, i can't get it to work right now.
 

Yes, I understand right now . Try this schematic from linear.com. If your opamp works, then we will investigate the integrator configuration.
 

Unfortunately, it doesn't work either, the output also saturates with some ripples around the Vdd
 

So there is a problem somewhere.

Run 1ms tran simulation without any feedback loop and with two 0.6 V voltage sources connected to your inputs and post the results.
 

Here are the test bench schematic, the transient output & the DC operating points also.

**broken link removed**

As u can see, the O/P is around 0.6 V as expected , however there is a huge spike at the end !! i don't know how it can get values by -600 Kilo Volts!! I believe it is from the vcvs, i am afraid that it may be the cause of all these problems, although i used it in that way 2 years ago and it worked.
**broken link removed**

**broken link removed**



-----
UPDATE:

Originally i inserted 1.2V as the maximum voltage value in the property of the vcvs, that resulted in the previous output.

Now that i removed it and left it blank , the new result has now glitch
 
Last edited:

Three attachments do not work . . .
 

Weird !! they all work for me now!


Test Bench Schematic



Transient output ( NO spike )


DC operating points

 

Really weird the problem with attachments. When they do not work there is only a link titled for example "Attachment 118516" that do not work. When they work there is a picture and its has a problem title like "dc-op-points.png".

Thanks for the pictures.

You plotted Vin+ and Vin-.
Please plot following plots on one picture:
1) From the testbench hierarchy (top level):
1.1) Vin+ and Vin- (as you plotted)
1.2) Vo+ and Vo-
1.3) gnd and vdd net (you can give them names)

2) From the opamp hierarchy:
2.1) Outputs of the first stage - they are not named (the outputs of the differential pair)
2.2) v_cmfb
2.3) common source for the input pair - it is not named
2.4) vmirror


I understand that it may seem as there is a lot not necessary plot, but believe me, it helped to analyse a lot of "problematic" circuits in this way. It is important to plot all of them using tran simulation.
 

I switched the polarity of the cmfb circuit (switched them in the vcvs) , i think this way it is a negative Feedback loop.
and here are the outputs

Figure 1




Figure 2




Op- Amp Level Schematic




Apparently , the vcmfb value is a big problem , it is unstable, however using stb analysis on the probe , it appears stable!!


I could limit the Vmax & Vmin of the vcvs to 1.2 & 0 respectively,
the new plot is still unstable, but of course the vcmfb saturates to 1.2 & 0 only.

 
Last edited:

Good move with CMFB. Now when you found it, it is clear that previously it was a positive loop. Nice!

Please, use much lower input signal frequency (now we have 10 MHz), for example 1 kHz. Additionally, introduce a delay time for the input signal. The delay may be 3 * period. For example:
- f_in = 1 kHz
- delay = 3 ms
- simulation time = 6 ms


Nice pictures! Now it is much clearer.
 

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