The estimation is valid for first order low-pass respectively system with dominant pole. To keep 500 ps rise time of a band limited input signal, the bandwidth must be higher than 700 MHz. Quadratic summation of risetimes can be a first estimation.
The estimation is valid for first order low-pass respectively system with dominant pole. To keep 500 ps rise time of a band limited input signal, the bandwidth must be higher than 700 MHz. Quadratic summation of risetimes can be a first estimation.
Yes, this estimation is only enough to keep more or less the same integrity for digital signals. Depending on the shape of rising/falling edge, more sidelobes should be included to get less distortion.
The input power is about 0dBm, with 10-12dB gain, the output power will be 10-12dBm. So I fully agree with FvM, MMIC amplifiers from Mini-Circuits are good candidates. They are much easier to use.
You haven't said anything about the application because similar has been done before with Logic in many different ways. ECL,PECL, CML,SAS,SATA,LVDS etc .
Do you care about jitter, equalization for losses on FR4, EMI, differential 50 Ohms? Impedance tolerance? Prop Delay? Return Loss? 25mV De-noise hysteresis? DC bias, ESD protection? Make,? buy? 1 or many? With Connectors? Evaluation Board? For Radar? for GPR? for Laser? etc etc?
LVDS Eval SN65CML100 can be configured to drive a dual 50-Ω load. In this configuration one 50-Ω resistor (tied to the termination voltage VTT) is placed near the output of the SN65CML100 and a second 50-Ω resistor (also tied toVTT) is placed near the end of the transmission line. 2 GBPS 1.4Vpp x2