Negneg
Newbie level 6
differences in NAND's parallel PMOSes' threshold voltage when swap inputs
Hi,
I'm running a NAND gate in HSpice, and I'm giving it different pulse source signals (different frequencies). Then, I'm running the MOSRA Aging simulator to calculate the threshold voltage changes of the two identical parallel PMOS transistors.
The results are fine for most of the signals, however I see some strange results for the cases when the frequencies are very different:
For example when input A has a pulse signal of: Vin1 In1 0 pulse (0 'Supply' 0 10p 10p 90p 200p)
and input B has the signal of: Vin2 In2 0 pulse (0 'Supply' 0 10p 10p 9990p 20000p)
The results show that the threshold voltage changes because of HCI (which is related to the number of transitions/switches) for input A is very high compare to input B, which is the correct answer! But, when I swap the inputs and run the NAND gate again (which should be exactly the same), I get strange numbers showing that the threshold voltage changes are much higher for the low frequency input (almost close to the high frequency values).
In summary I see a difference between these two cases:
Vin1 In1 0 pulse (0 'Supply' 0 10p 10p 90p 200p)
Vin2 In2 0 pulse (0 'Supply' 0 10p 10p 9990p 20000p)
and
Vin1 In1 0 pulse (0 'Supply' 0 10p 10p 9990p 20000p)
Vin2 In2 0 pulse (0 'Supply' 0 10p 10p 90p 200p)
Anyone has an idea why this is happening? Both PMOS are exactly the same in the HSpice code.
Thanks
Hi,
I'm running a NAND gate in HSpice, and I'm giving it different pulse source signals (different frequencies). Then, I'm running the MOSRA Aging simulator to calculate the threshold voltage changes of the two identical parallel PMOS transistors.
The results are fine for most of the signals, however I see some strange results for the cases when the frequencies are very different:
For example when input A has a pulse signal of: Vin1 In1 0 pulse (0 'Supply' 0 10p 10p 90p 200p)
and input B has the signal of: Vin2 In2 0 pulse (0 'Supply' 0 10p 10p 9990p 20000p)
The results show that the threshold voltage changes because of HCI (which is related to the number of transitions/switches) for input A is very high compare to input B, which is the correct answer! But, when I swap the inputs and run the NAND gate again (which should be exactly the same), I get strange numbers showing that the threshold voltage changes are much higher for the low frequency input (almost close to the high frequency values).
In summary I see a difference between these two cases:
Vin1 In1 0 pulse (0 'Supply' 0 10p 10p 90p 200p)
Vin2 In2 0 pulse (0 'Supply' 0 10p 10p 9990p 20000p)
and
Vin1 In1 0 pulse (0 'Supply' 0 10p 10p 9990p 20000p)
Vin2 In2 0 pulse (0 'Supply' 0 10p 10p 90p 200p)
Anyone has an idea why this is happening? Both PMOS are exactly the same in the HSpice code.
Thanks