2 dimentional array memory declaration

need help:verilog ram

i tried run this program but there's an error because of memory:multiple constant drivers.anyone can help me???

input WEN, A0, A1 ;

input DI0, DI1, DI2, DI3 ;

output DO0, DO1, DO2, DO3 ;


parameter MEMORY_SIZE = 4 ;
parameter WORD_LEN = 4 ;
parameter ADDRESS_WIDTH = 2 ;

reg [0 : (WORD_LEN - 1)] memory [(MEMORY_SIZE - 1) : 0] ; // the ram memory

wire [(ADDRESS_WIDTH -1) : 0] rw_address_reg ; // 'RD' (read) address port.

wire [0 : (WORD_LEN - 1)] bdi_data_reg ; // input 'data' register.

wire [0 : (WORD_LEN - 1)] ado_data_wire ; // output 'data' register

reg [0 : (WORD_LEN - 1)] ado_data_reg ; // output 'data' register

reg [(MEMORY_SIZE - 1) : 0] tempi ;

buf ira0 (A0_BUF,A0);
buf ira1 (A1_BUF,A1);

buf dib0 (DI0_BUF,DI0);
buf dib1 (DI1_BUF,DI1);
buf dib2 (DI2_BUF,DI2);
buf dib3 (DI3_BUF,DI3);

buf wenable (WEN_BUF, WEN);

assign
rw_address_reg={ A1_BUF,A0_BUF },
bdi_data_reg={ DI0_BUF,DI1_BUF,DI2_BUF,DI3_BUF } ;



always @(negedge WEN_BUF)
begin
if (WEN_BUF == 1'b0)
begin
if (rw_address_reg < MEMORY_SIZE)
begin
memory [rw_address_reg] = bdi_data_reg ;
ado_data_reg = memory [rw_address_reg] ;
end

else
begin
$display("WRITE-ERROR [RAM4X4]: [ Illegal Address A<1:0> = %d > %d ], time = %d\n", rw_address_reg, MEMORY_SIZE, $time);
for (tempi = 0; tempi < WORD_LEN; tempi = tempi + 1)
begin
ado_data_reg[tempi] = 1'bx ;
end
end
end
end

always @(rw_address_reg)
begin
if ( WEN_BUF == 1'b1)
begin
ado_data_reg = memory [rw_address_reg] ;
end

else
begin
for (tempi = 0; tempi < WORD_LEN ;tempi=tempi+1)
begin
ado_data_reg[tempi] = 1'bx ;
end
$display("WRITE-ERROR [RAM4X4]: A<1:0> changed at ",$time," while (WEN) = 0\n");

for (tempi = 0; tempi < MEMORY_SIZE; tempi=tempi+1)
begin
memory[tempi] = 4'bx ;
end
memory [rw_address_reg] = bdi_data_reg ;
ado_data_reg = memory [rw_address_reg] ;
end
end

always@(bdi_data_reg)
begin
if ( WEN_BUF == 1'b0 )
begin
memory [rw_address_reg] = bdi_data_reg ;
ado_data_reg = memory [rw_address_reg] ;
end
end

Re: need help:verilog ram

You are not allowed to write to a 'reg' type in 2 different prodedural blocks.
You have written to 'ado_data_reg' in 2 always blocks, which is a contention. It is creating 2 drivers for it, hence the error.
Kr,
Avi
http://www.vlsiip.com

Re: need help:verilog ram

so i need to modified in the different blocks for ado_data_reg?

Re: need help:verilog ram

write to 'ado_data_reg' only in one always block. i.e you will have to combine the 2 always blocks
Kr,
Avi
http://www.vlsiip.com

Re: need help:verilog ram

i dont understand.for example?

Re: need help:verilog ram

ado_data_reg = memory [rw_address_reg]

The above means, that you are 'writing' a value to 'ado_data_reg'.

And you are writing a value to ado_data_reg in 2 different always blocks.
If you think the always block as a combinational cloud(thats what it represents in the absence of any poseedge in its sensitivity list), then effectively you have 'ado_data_reg' coming from 2 combinatinal clouds and shorted togegher. This is a poor design, which clearly wont' work.
So DO NOT ASSIGN or 'WRITE' TO A 'reg' type IN MORE THAN ONE ALWAYS BLOCK.

Hope it helps,
Kr,
Avi
http://www.vlsiip.com