rmawatson
Newbie level 2
![Newbie level 2](/styles/images/ranks/alevel2.gif)
Hello,
I just wanted to check if there are likely to be any problems interfacing the following clock fanout ( https://www.ti.com/lit/ds/symlink/sn65lvds104.pdf ) which is 3.3v with 2.5v driver from my FPGA.
The differential specifications seem fine for both reciever and trasmitter
My concern is with the "Fail Safe" 300k pull-ups on the Receiver that will pull the lines high when not driven. Is this going to cause any issues to the driver. the 3.3 v is well within the absolute maximum (3.6) of the drivers device pins, but I don't know if there is any problem at all with the differential driver of the FPGA seeing 3.3v on the pin when it is switched on.
Thanks for any assistance.
I just wanted to check if there are likely to be any problems interfacing the following clock fanout ( https://www.ti.com/lit/ds/symlink/sn65lvds104.pdf ) which is 3.3v with 2.5v driver from my FPGA.
The differential specifications seem fine for both reciever and trasmitter
My concern is with the "Fail Safe" 300k pull-ups on the Receiver that will pull the lines high when not driven. Is this going to cause any issues to the driver. the 3.3 v is well within the absolute maximum (3.6) of the drivers device pins, but I don't know if there is any problem at all with the differential driver of the FPGA seeing 3.3v on the pin when it is switched on.
Thanks for any assistance.