Hi. I had taken a look at your spec/abstract. You should have some basic PLL parameter to start off your design.
Since you are designing a fixed frequency PLL, presumably you are not concerned about switching speed, but what about yout reference spur suppression, and phase noise requirement.
About your VCO design, things such as VCO tuning voltage level will design your loop filter topology.
Assume some basic spec for your PLL, for eg
Reference spur suppression @100MHz offset: XdBc
Phase Noise
@ 1KHz : -X1dBc/Hz
@10KHz : -X2 dBc/Hz
@100KHz -X3dBc/Hz
@1MHz -X4dBc/Hz