1st order sigma delta output is wrong verilog Cadence

[InvokeMeWell]

hello all,


below is the code of sigma delta 1 st order,
the clock is 1.25GHz, the fractional word (static does not change) I put e.g. 0.34*2**8 (fractional to binary)
and i get the average of sigma delta ( otw_f) 0.266 which is off i tried more bits, but did not succeed!!
could anyone help me? I simulate in cadence

thank you in advance

 

[FvM]

Looks good, why not registering output bitstream otw_f? I guess problem is in your testbench, how do you measure otw_f density?

 

[InvokeMeWell]

I tried 2 solutions,
1)the first was the stupud method to get an average of the otw_f
2)the second I put a passive RC filter with R = 5 & n = 10nF, but still was no the same and I am puzzled.
do you have any test bench to propose?

 

[FvM]

You are apparently performing test in real hardware. In this case registering otw_f is mandatory to avoid effects by adder timing. What's the result with digital density measurements, e.g. count '1's?

 

[InvokeMeWell]

is not in real hardware, I just simulate them i ncadence, because afterwards I want to "put" this mash in a adpll.
I dont have done the count'1 s a presume I should have done it.............
and the sum of 1 what I could do them after afterwards?