Combination logic between source & synchronizer flops

[sakshi gupta]

combinational logic between source & synchronizer flop will decrease MTBF as frequency of data change at the input of first flop of the double flop will increase .
Can anybody update me how it will result in glitch :?:

 

[FvM]

Are you asking about gliches in the logic output or failure of synchronization due to metastability?

 

[sakshi gupta]

Yes, can you illustrate me with example how combo logic b/w the source flop output & input of the first flop of the double flop synchroniser can result in glitch ?

 

[FvM]

Particularly logic implemented in programmable LUT of FPGA must be exected to glitch, if more than one input signal is changing at the same time due to delay skew. With transistor level ASIC logic, it may possibly occur in a few cases and you should be able to predict the risk based on your knowledge of the exact gate level circuit.

As a simple example, assume an input vector changing from "01" to "10", e.g. a 2-Bit counter. The logic output is expected to stay '0' but would be '1' for other input codings. If the input is affected by delay skew, the output will glitch. If only one source signal is switching, it may be, that multiple intermediate signals change, depending on the logic implementation.

 

[sakshi gupta]

You mean to say that it is possible that mutiple inputs of the combinational logic might be affected by the delay skew resulting in Glitch

I think there will be no issue combinatorial logic between source & synchronizer flop is equivalent to buffer ?