How to stop the simulation in VHDL TB

[Mkanimozhi]

Hi Experts,
I need to stop the simulation in through VHDL Test bench, Like we have $finish system task we have anything in VHDL ? How can we achieve this one ?


Thanks and regards,
Kanimozhi.M

 

[Dave_PL]

CLK_GEN: process
begin
		 
	if ENDSIM=false then
		CLK <= '0';
		wait for CLK_PERIOD/2;
		CLK <= '1';
		wait for CLK_PERIOD/2;
	else
		wait;
	end if;		
end process;
		
STIM: process
begin
	-- your stim
	ENDSIM := true;
	wait;			
end process STIM;

ENDSIM is shared variable of boolean type initialized to false;

Hope this helps.

 

[TrickyDicky]

There are many way to stop a simulation from VHDL.

The easiest way is to use an assert:

assert false report "Simulation Finished" severity failure;

report can also be used with an "if" if you dont like the reverse nature of assert.

if something_happened then report "Simulation finished" severity failure; end if;

The "recommended" way to end a simulation when everything has gone correctly, is to halt all stimulus. This will be stopping the clock like in Dave's post above, but also putting any input processes into a never ending wait if they do not use the generated clock.

in VHDL 2008, they have introduced and new package called env to the std library, with procedures called stop and finish, that act like $finish in verilog.

so you can just use:

library std;
use std.env.all;

.......
stop(0);
--or
finish(0);

-- For both STOP and FINISH the STATUS values are those used
  -- in the Verilog $finish task
  -- 0 prints nothing
  -- 1 prints simulation time and location
  -- 2 prints simulation time, location, and statistics about
  --   the memory and CPU times used in simulation

  -- Other STATUS values are interpreted as 0.

 

[shnain]

Hi,

Check out the following link :

**broken link removed**

Yours,

 

[Alexium]

Hi,

Check out the following link :

**broken link removed**

Yours,

Thank you for the link .

 

[alexan_e]

I like to use a clock with specified length

clk_process :process
        begin
          for Z in 1 to 800000
          loop
            clk  <= '1'  ;
            wait for 5 ns; -- half period
            clk  <= '0'  ;
            wait for 5 ns; --half period
         end  loop;
          wait;
        end process;

or you can use this to run for a specific duration

stop_simulation :process
begin
	wait for 100 ns; --run the simulation for this duration
	assert false
		report "simulation ended"
		severity failure;
end process ;

Alex

 

[TrickyDicky]

if we're gonna post what we all like to do:

I set TIMEOUT as a generic on the testbench so I can modify it from a TCL script, or just modify the source at the top of the file and not have to find my clock process.

------------------------------------------------------------------------------------------------
  --clk_proc : process to generate the clock
  ------------------------------------------------------------------------------------------------
  vid_clk_proc : process
    variable end_time       : time;
  begin
    while not ENDSIM loop
      
      clk                    <= not clk;
      
      if NOW >= TIMEOUT*CLK_PERIOD then
        KILLSIM               <= true;
      end if;
      
      if run_clk then
        wait for CLK_PERIOD/2;
      else
        wait until run_clk;
      end if;
    end loop;
    
    if KILLSIM then
      report "Simulation Timed Out after " & integer'image(TIMEOUT) & " clock cycles."
        severity warning;
        
    else
      end_time := NOW;
      
      report "Simulation ended successfully after " & time'image(end_time)
        severity note;
        
    end if;
    
    wait;
  end process;
  
  -------------------------------------------------------
  --Initial reset to setup all registers and memories
  -------------------------------------------------------
  reset <= '1', '0' after RESET_PERIOD*CLK_PERIOD;
	
	
  --------------------------------------------------------------------
  --Stop all processes to starve all events and stop the simulation
  --------------------------------------------------------------------
  ENDSIM <=    KILLSIM 
            or (input_complete and output_complete);

I almost never have a process sensitve to clock in the testbench, I have them in a while loop watching ENDSIM (like the clock process above) so I can divert all processes to wait to halt.