Timing analysis and FPGA's

[vaisram]

Hi all.. I am a newbie and I require answers to a few questions posted below:
1. How are timing constraints developed and what are the steps followed for timing closure?
2. What is a clock gate and why is that done?
3. In working with multiple clocks, which is hte best method to synchronize control paths and data paths across multiple clock domains?
4. When do we go for an ASIC design and when to got for FPGA's?
5. How do we choose an FPGA? Are there any generic rules or is it based on the design?

 

[shitansh]

Let me try to give answer of questions one by one. Since quite busy schedule for me I will try to answer your question per day.

I hope my answer will help you. Please others also put some lights on these questions since these all are very fundamental, essential questions need to know for new engineers.

1. How are timing constraints developed and what are the steps followed for timing closure?

To ensure that your design can operate safely at rated speed, you need to perform timing analysis for your design either by timing simulation or by static timing analysis.

Now to perform static timing analysis you need to give proper timing constraint to your design, because timing analysis tool will not perform timing check on path for which you have not given any constraint. In short you need to build a STA environment for your design to perform timing analysis.

Now come to your question how to build proper STA environment or How timing Constraint developed to perform or to guide timing tool to do proper analysis?

Well, for this you need to give constraint which can be divided in two parts.
(1) INTERFACE CONSTRAINT
(2) DESIGN INTERNAL CONSTRAINT

Lets talk about Design internal constraint first. For any and all digital design will consisted of four kind of timing path which are (a) flip fop to flip-flop path (b) input-port to input of flip-flop path (c) output of flip-flop to output port and (d) input port to output port

once you give clock constraint for your design all flip-flop to flip-flop path will be constraint and all path (a) will be analyzed with your clock constraint. Again for multi clock design you need to give proper clock constraint like generated clock, derived clock..etc. in short for all FF to FF path clock constraint is one parameter.
Apart from this by knowing your design you need to setup exceptional path to guide timing tool like false path, single cycle/multi-cycle paths..etc

Now rest constraints for paths (b), (c) and (d) will depends on Interface environment for your design. Again you need to know your design, means how your design is going to interface with external words and according to that you need to give interface constraint for your design with respect to either virtual clock or clock of your design. And these constraints are Input delay specification for setup and hold, output delay specification for setup and hold

Since this is not complete answer but I am sure that from this point and with this back ground you can move ahead

HTH,
Shitansh Vaghela

 

[sameh_yassin99]

Hello,
Dear Vaisram,Shitnash,
The answer for question 2 is :
Clock Gating Meaning:
Sometimes we need to stop the clock signal from entering certain module for two things. First we may need to stop the function of that module such as a counter that has reached maximum. Second we need to stop the clock for power consumption saving.
How to accomplish it
The simplest way is to use 2-input and gate, one input is the clock while the other is an enable signal. However, the synthesizes tool such as XST of xilinx will output a warning about that, because this solution may lead to glitches.
A better way
You may use register with enable signal. When you need to "turn off" the output of that register, disable the enable signal. Clock gating is a pretty famous topic and you can find many good solutions for it. A canditate can be found here**broken link removed**.

regards,
S. Yassin