How to choose the MOM capacitor for 10 bit SAR ADC

[howardtang85]

I am currently designing a 10-bit Charge-Redistribution SAR ADC. I will be using MOM capacitors to form the Capacitive DAC since MOM offer smaller capacitance and hence, smaller power consumption.

However, does any one know which configuration of MOM capacitor is better for the design? For example, how many metal layer, metal length, asymmetry design (extra metal layer to shield from substrate), symmetry design?

In addition, I found that there are 3 terminal for a MOM capacitors, in which, one connected to the top plate, one connected to the bottom plate, and last one to the substrate. Does anyone know the substrate terminal should connected to what potential and what purpose it serve?

Thanks!

 

[erikl]

May be this EE240 homework solution is helpful: View attachment MOM-cap_calculation.pdf.
Connect the 3rd terminal (substrate) to GND/VSS.

 

[howardtang85]

Thanks for the reply!

By the way, may I know how does a Vertical Parallel Plate capacitor looks like?

 

[erikl]

See here: View attachment cap_alternatives.pdf
Metal-metal or Multi-layer, with or without poly usage.