[SOLVED] Disable timing check for sync flops in vcs

[chipmonkey]

Hi,

I'm doing a gate-level simulation with SDF using vcs. I want to disable the timing checks on the synchronisation flops alone.

How to do this? Is there any vcs option?

 

[phixcoco]

I'm not familiar with vcs. But i would probably **** into the standard cell that used, and comment out $setup, $hold etc lines within specify block of Flop models under concern.

- phixcoco

 

[chipmonkey]

I'm not familiar with vcs. But i would probably **** into the standard cell that used, and comment out $setup, $hold etc lines within specify block of Flop models under concern.

- phixcoco

But the issue here is that the same cell is being used as sync flop as well as normal flops. so commenting the specify would affect the normal flops too.

 

[phixcoco]

But the issue here is that the same cell is being used as sync flop as well as normal flops. so commenting the specify would affect the normal flops too.

'synchronization flop' is ambiguous, i thought you were mentioning all DFF w/o async set/reset...

So, I think the following page might be useful. It intends to disable timing check on specific instance selectively and could be a solution for u:
Disable timing check selectively

And pls wait for others to reply with a possible simpler solution!

- phixcoco

 

[chipmonkey]

@phixcoco: I tried what is described in the link provided. But dint quite work out as I was getting compilation error

However, found this VCS run time option that helped

You can use tcheck command in ucli prompt and disable or enable timing check upon
a specified instance/port at runtime.

tcheck -help in ucli prompt gives the details about the command as shown below:
************************************
tcheck disable/enable timingcheck upon a specified instance/port at runtime
usage:
tcheck <instance|port> <tcheck_type> <-msg|-xgen> [-disable|-enable] [-r]
where <instance|port> is a hierarchical full path name of an instance or port
<tcheck_type> is one of [all|HOLD|SETUP|SETUPHOLD|WIDTH|RECOVERY|REMOVAL|RECREM|PERIOD|SKEW],
which is used to indicate which type of timing check we want to change
<-msg|-xgen> controls simulation behavior when a timing check violation is detected
-msg disable/enable timing violation warning on the specified instance or port
-xgen disable/enable notifier toggling on the specified instance or port
[-r] change all timing checks for specified instance and all sub-instance recursively
[-disable|-enable] turn off/on timing check according to the above constraints (by default, all timing checks are enabled)
****************************************

 

[ljxpjpjljx]

you can let designer to list all the cross-clock-domain flip-flops ,then add them with option tcheck for vcs!

 

[chipmonkey]

you can let designer to list all the cross-clock-domain flip-flops ,then add them with option tcheck for vcs!

Yes.. thts what i did.. thanx ljxpjpjljx and phixcoco:razz: