how to change verilog code to VHDL code

[reef88]

hi,

can someone in this forum convert verilog code to vhdl code..please...

this is the code:

module CLK_DIV(
input CLK,
output reg CLK_DIV=0
);


reg [1:0] REGISTER=0;
always@(posedge CLK)
begin
REGISTER<=REGISTER+1;


if(REGISTER==4'b00) //creates a 0.04us 25MHz

begin
CLK_DIV <= ~CLK_DIV;
REGISTER<=0;
end
else
CLK_DIV <= CLK_DIV;

end

endmodule

 

[ravics]

Clock_Division_By_2 : process(clk) -- 50MHz clock (20 ns)
begin
if rising_edge(clk) then
clk_25MHz <= not clk_25MHz; -- 40 ns divided clock
end if;
end process Clock_Division_By_2;

You have to initialize clk_25MHz i.e. before architecture block u have to declare
signal clk_25MHz : std_logic := '0';

 

[reef88]

thanks for helping me ravics...

i already try this code and try to run in ise xilinx 10.1 and it is successfully..

is this true code for vhdl?
can anyone valid it?

this is the code:


entity CLK is
Port ( CLK : in STD_LOGIC;
CLK_DIV : out STD_LOGIC);
end CLK;


architecture Behavioral of CLK is

signal clk_25MHz : std_logic := '0';

begin

process(clk)

begin

if rising_edge(clk) then
clk_25MHz <= not clk_25MHz; -- 40 ns divided clock
end if;

end process;

end Behavioral;

 

[TrickyDicky]

Yes it is correct, but I wouldnt divide a clock like that in any language. You're bound to have timing errors.
Either use a PLL or generate a clock enable with all registers runnings at the source clock frequency.

 

[reef88]

but it seem not correct if we view in RTL schematic in xilinx ise software...
RTL schematic using verilog code not similar with vhdl code...

verilog code RTL schematic like this:




can anyone convert this verilog code to vhdl code similar with the schematic diagram above?

 

[std_match]

can anyone convert this verilog code to vhdl code similar with the schematic diagram above?

It doesn't work.
The 2-bit counter REGISTER will be frozen at zero.
The code from ravics will generate the same output.

 

[reef88]

it'ok if it doesn't work....
just convert this verilog code to vhdl code similar with the schematic above please...
i just want to try it...

 

[ravics]

It doesn't work.
The 2-bit counter REGISTER will be frozen at zero.
The code from ravics will generate the same output.

I had just given the direct conversion of verilog to vhdl. Didn't give optimized code for perfect operation.

 

[reef88]

if there are any vhdl code for clk div for vga controller?
i need this vhdl code please...

 

[jducluzeau]

Reef88,

Ihave some question to your verilog code.
1/First this is not a clock divided by 2 but by 4 due to REGISTER[1:0] reg. the duty cycle is 25% and not 50%. Is it what you want?
2/At the line if(REGISTER==4'b00) what do you compare REGISTER which have 2 bits to 4 bits?
3/ When REGISTER==4'b00 you initialize REGISTER=0; Does it make sense? Is there no overflow?
4/ else statement is it really necessary?

Then what do you want your code does exactly?

your code in vhdl could be :


entity CLK is
Port ( CLK : in STD_LOGIC;
CLK_DIV : out STD_LOGIC);
end CLK;


architecture Behavioral of CLK is

signal clk_25MHz : std_logic := '0';
signal REGISTER :std_logic_vector(1 downto 0):="00";

begin

process(clk)

begin

if rising_edge(clk) then
REGISTER<=REGISTER+1;
if (REGISTER=="00") then
clk_25MHz <= not clk_25MHz; -- 40 ns divided clock
end if;
end if;

end process;

end Behavioral;

 

[reef88]

To jducluzeau,

yup..a clock divided by 4 because i want 25MHz clock
yup...the REGISTER is 2 bits to 4 bits

actually this clk code is for vga controller to display 8 difference color using 3 bits input...
so i want this clock verilog code convert to vhdl code...

i already try your code in xilinx ise software...
but it has error on it...it say unexpected REGISTER, expecting error or IDENTIFIER and unexpected IF, expecting PROCESS..
can you fix it?...please

 

[std_match]

"register" is a reserved word in VHDL, so you must use another name.

 

[reef88]

To std_match,
so if the register can't use...what another name can be use?
can you included with example please...

 

[permute]

the code looked the same. The verilog code takes the register and on any given cycle will either add or reset the value. if the value is currently 0, then the value will be reset to 0. if the value is not 0, 1 is added each cycle until an overflow. if the counter is currently 0, then the clk_div output is inverted.

If you had tried a direct code conversion, keep in mind that VHDL will allow a comparison to a constant vector of the wrong size. Such a comparison will be false. The tools will actually give a warning for that.

so the original code should perform a clock division by 2. The schematic that "doesn't work" also shows this. The output of the NAND becomes a 1, the inverter makes it a 0, and the counter has an active low reset. The input to the fde is not q, and the ce line is driven to a 1, so it toggles.

It is still good practice to use the built in clocking resources where possible. 25MHz probably isn't fast enough to be an issue though.

the block should have something like:
cnt <= cnt+1; -- signal cnt : unsigned(1 downto 0) := (others => '0');
clk_div <= cnt(cnt'high);

this gives a 50% duty ratio with a divide by 2^n. It is based on the counter naturally overflowing. If you want to divide by 2,4,8, ect... you can do this by changing the counter size.

 

[reef88]

To permute;

thanks for the info...
can you give example vhdl code for clock division of 50MHz to 25MHz?...please..

 

[permute]

clk_div <= not clk_div

 

[reef88]

hi permute,
can you give the overall vhdl code for 50MHz to 25Mhz for clock division...
so i can try on the ise xilinx...please..

 

[sdhnain]

hi permute,
can you give the overall vhdl code for 50MHz to 25Mhz for clock division...
so i can try on the ise xilinx...please..

Hi,

here is the code of the divider by 2:

entity clk_div is
Port (
  in_rst_n : in STD_LOGIC;
  in_clk_50MHz : in STD_LOGIC;
  out_clk_25MHz : out STD_LOGIC);
end clk_div;


architecture synth of clk_div is

signal sig_clk_25MHz : STD_LOGIC;

begin

process(in_rst_n, in_clk_50MHz)

begin

  if in_rst_n = '0' then
    sig_clk_25MHz <= '0';

  elsif rising_edge(in_clk_50MHz) then
  
    if sig_clk_25MHz = '0' then
      sig_clk_25MHz <= '1';
    else
      sig_clk_25MHz <= '0';
    end if;

  end if;

end if;

end process;

out_clk_25MHz <= sig_clk_25MHz;


end synth;

 

[reef88]

thanks in advance to sdhnain...

i have try your code...it works...:lol:

 

[rohan_vlsi]

here ur clk has been created in vhdl


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rply is
Port ( clk,reset : in STD_LOGIC;
CLK_DIV : out STD_LOGIC);
end rply;

architecture Behavioral of rply is
signal register1 : std_logic_vector(1 downto 0):= "00";
signal CLK_DIV1 : std_logic;
begin


process(clk)
begin


if(reset='1')then
CLK_DIV1<='0';

elsif(rising_edge(clk))then
register1<=register1+1;

if(register1="00") then---------creates a 0.04us 25MHz

CLK_DIV1 <= not CLK_DIV1;
else
CLK_DIV1 <= CLK_DIV1;

end if;
end if;
end process;

CLK_DIV<=CLK_DIV1;


end Behavioral;