DNL measurments and calculations

[zvilupu]

Hi all,

after reading the threads regarding INL/DNL i still dont understand something:

i'm simulating a single-slope 12 bit ADC. does it means that for calcuating the DNL i need to run the simulation >(2^12) ?
when i measure INL i simply do an input sweep of ~10 point (from min to max) and calculate the INL (i know it an interpolation...).
but as DNL definition, do i need to calculate each digital code????

i come across the thread: https://www.edaboard.com/threads/188527/
how many samples does i need to input (and in what spread) to use the matlab code of: **broken link removed**


Thanks in advance...

 

[JoannesPaulus]

you actually need many more than 2^12... I would guess in the order of 500ksamples...

 

[erikl]

... how many samples do i need to input ...

you actually need many more than 2^12... I would guess in the order of 500ksamples..

I think JoannesPaulus is right. See this Maxim Application Note:
View attachment Histogram_Testing_DNL_INL_of_ADCs.pdf

 

[zvilupu]

erikl & JoannesPaulus, thanks for your answer.
every run in the spectre simulation takes ~40sec.
because i simulate 11.5 bit (3000 steps) and i took every step of samples as ~100uV. this will give me a minimum step of 0.15LSB and with resolution of ~14.2 bit.
for this run i nedd approx. ~40000 semples with means long time. your suggestion for taking ~0.5M semples will take me months...
have any idea how to do it ??

thanks!

 

[erikl]

... your suggestion for taking ~0.5M semples will take me months...
have any idea how to do it ??

If you have access to a farm of computers you can run the simulations in parallel, this will break down the runtime down to weeks or even days.

Otherwise you could run the DNL/INL analysis in time domain mode: Simulate (say) 2³=8 full scale sine waves with about 2^n samples per sine wave length (it is important that the sample and the sine frequencies be mutually prime). By this you need to simulate just 2^(n+3) samples, and you'll receive results which will give you quite a good idea about the DNL/INL behavior vs. code, s. the picture below:

 

[JoannesPaulus]

@erikl: the method you mention is totally new to me and could potentially cut simulation time by a huge amount. Do you have any reference I could use to learn how to choose the number of sine waves wrt the number of bits, for instance (your choice of 8 seems somewhat arbitrary). Thank you!

@zvilupu: Not having known erikl's method, I always avoided DNL/INL simulations for ADCs with more than 9 bits (due to the looong simulation time required). You can still get a lot of information from the dft of the output and looking at the error of a modulo-time plot.

 

[zvilupu]

thanks or your quick answers.
erik:it sounds interensing but as JoannesPaulus wrote, what is the method to choose the number of sin waves ? another thing is if i choose 8 sin waves (with FS=2V) the total number of samples (for a 12 bit ADC) will be 2^(12+3)~33k samples. ??

JoannesPaulus: what informationcan i get from the dft of the output? what output are you talking about? because i'm runinng the comparator and simply get a digital signal that is change. are you referring to this? what are you meant in "looking at the error of the modulo-time plot"?

another question: if i will do a ramp of ~40k steps, why it is not right? because of the "confidence precent"?

thanks alot...again!

 

[erikl]

Re: DNL simulation in time domain

@erikl: the method you mention is totally new to me and could potentially cut simulation time by a huge amount. Do you have any reference I could use to learn how to choose the number of sine waves wrt the number of bits, for instance (your choice of 8 seems somewhat arbitrary).

erik:it sounds interensing but as JoannesPaulus wrote, what is the method to choose the number of sin waves ? another thing is if i choose 8 sin waves (with FS=2V) the total number of samples (for a 12 bit ADC) will be 2^(12+3)~33k samples. ??

I just used the method suggested by this **broken link removed**, s. only the short paragraph "Generic Setup for Testing Static INL and DNL" (p. 3). For the high-accuracy DAC, an ideal DAC (functional/behavioral) can be used.

The intention - why the sample and the sine frequencies should be prime to each other - results in different sample points on the sine wave - if you sample more than one wavelength. I.e. as more sine waves you sample, as more different points on the sine wave you convert, and thus you include the quantization noise (½ bit) into the DNL result (which may be subtracted for the real DNL definition).

Of course the choice of the number of sine waves to be analyzed is arbitrary; more statistic results just increase the confidence level, or - differently expressed - the accuracy.

 

[JoannesPaulus]

JoannesPaulus: what information can i get from the dft of the output? what output are you talking about? because i'm runinng the comparator and simply get a digital signal that is change. are you referring to this? what are you meant in "looking at the error of the modulo-time plot"?

I am referring to the output of the ADC, of course. From the dft you can get, SNR, SNDR, THD, SFDR (somewhat representing your INL). In this case, if you choose your input frequency correctly (i.e. use coherent sampling), you need fewer samples to get a rather accurate estimate of the performance of your design.

 

[zvilupu]

I am referring to the output of the ADC, of course. From the dft you can get, SNR, SNDR, THD, SFDR (somewhat representing your INL). In this case, if you choose your input frequency correctly (i.e. use coherent sampling), you need fewer samples to get a rather accurate estimate of the performance of your design.

what do you mean "choose the input frequency correctly"? do you mean that i need to insert a periodic signal to the input (like a sin wave??). i'm asking that because in my simulations i'm runing only the comparator (the input signal is like a DC, i.e. after S&H). can you explain to me (if you can a step-by-step) how to find the dynamic parameters and to do thoes dynamic testing.

regarding to the DNL/INL test. i'm sampling ~40k sampling (i have 3000 steps~11.5 bit), so my resolution is ~15.2 bit. what i need to do with this data-base in order to get to the DNL? do i just transfer it to matlab and process the matlab script attached before??

---------- Post added at 23:44 ---------- Previous post was at 23:27 ----------

If you have access to a farm of computers you can run the simulations in parallel, this will break down the runtime down to weeks or even days.

Otherwise you could run the DNL/INL analysis in time domain mode: Simulate (say) 2³=8 full scale sine waves with about 2^n samples per sine wave length (it is important that the sample and the sine frequencies be mutually prime). By this you need to simulate just 2^(n+3) samples, and you'll receive results which will give you quite a good idea about the DNL/INL behavior vs. code, s. the picture below:
View attachment 49770

is there's a chance you can send me the script for your INL/DNL (the one you created the figures you attached..)??

 

[erikl]

is there's a chance you can send me the script for your INL/DNL (the one you created the figures you attached..)??

No script, sorry! This has all be done manually within SPECTRE's ADE and its calculator - years ago. But it's easy: just plot the DNL results (ADC-output re-converted by an ideal DAC into an analog value - ADC-input) vs. transient sim. time.

 

[zvilupu]

No script, sorry! This has all be done manually within SPECTRE's ADE and its calculator - years ago. But it's easy: just plot the DNL results (ADC-output re-converted by an ideal DAC into an analog value - ADC-input) vs. transient sim. time.

my problem is because my ADC has ~3000 steps (with FS=2V--> ~670uV for each step) how can i do an ideal DAC that does 3000 steps (~11.55 bits).
any reply regarding the dynamic tests olso??

thanks!!

 

[zvilupu]

what is the input for the ADC to find the dynamic parameters? what im asking is what input should i use to the ADC (sin wave? in what freq? a ramp? or simply a DC?) and how much samples do i need?

thanks!

 

[JoannesPaulus]

what do you mean "choose the input frequency correctly"? do you mean that i need to insert a periodic signal to the input (like a sin wave??). i'm asking that because in my simulations i'm runing only the comparator (the input signal is like a DC, i.e. after S&H). can you explain to me (if you can a step-by-step) how to find the dynamic parameters and to do thoes dynamic testing.

Yes, once you have designed the ADC, you will need to run simulations using sine waves. Of course, for a dual-slope ADC you can make sure that the comparator is good enough checking the offset, accuracy and so forth but you must still simulate the effect of all the other components (current sources, capacitors, reset circuit...). In order to correctly simulate the SNR, I suggest you choose a frequency (f) with the following formula: f=D*fs/2^N, where D is a suitable odd number, fs is the sampling frequency and 2^N is the number of samples.
For the reasons of this formula, search "coherent sampling".

regarding to the DNL/INL test. i'm sampling ~40k sampling (i have 3000 steps~11.5 bit), so my resolution is ~15.2 bit. what i need to do with this data-base in order to get to the DNL? do i just transfer it to matlab and process the matlab script attached before??

yes.

is there's a chance you can send me the script for your INL/DNL (the one you created the figures you attached..)??

You should search for Boris Murmann web site. He has a matlab code that generates the DNL/INL plots.

---------- Post added at 22:00 ---------- Previous post was at 21:56 ----------

what is the input for the ADC to find the dynamic parameters? what im asking is what input should i use to the ADC (sin wave? in what freq? a ramp? or simply a DC?) and how much samples do i need?

See my answer above.
Moreover, your ADC has must have some input frequency range requirements (even 0Hz is a frequency!). You should run simulations, at least at the bottom of your range, in the middle and at the top.

 

[erikl]

my problem is because my ADC has ~3000 steps (with FS=2V--> ~670uV for each step) how can i do an ideal DAC that does 3000 steps (~11.55 bits).

Use an ideal 12bit DAC with FS=4096×670µV=2.74V