Searching for JFET with separate Bulk pin and data on bulk voltage effects available

[Schmocki]

Hi,

does anyone know a JFET with separate Bulk pin (maybe like the 2N4220/1/2) where there are data available on the effect of non-zero bulk-source-voltage on drain current, transconductance...?

Best Regards,
Schmocki

 

[FvM]

I fear, you're searching a phantom device.

A planar JFET is made by "building" the channel with it's source and drain contacts on top of the gate. In so far there's no room for a bulk contact. If you would have another junction isolated substrate below the gate, it has no electrical effect on the transistor, except for causing gate leakage currents. Low leakage JFET structures in ICs are usually dielectrically isolated for this reason.

You can refer to semiconductor design text books or data sheets with chip layouts to verify this.

 

[Borber]

Such jfet does not exists. 2N4220 is packed into TO-72. It is metal can with it's own pin for grounding. Such jfet's are used at RF.
Some old mosfets like 3N128, 3N142, 3N143 (RCA) had that what you wish. It is single gate mosfet.

 

[Schmocki]

Hi,

I thought the 2N4222 had substrate/bulk connected to the case pin.

And the question is regarding discrete n-channel single gate junction fet built on a P substrate with a P gate where the substrate-channel junction acts as a bottom gate.

@Borber
I am only looking for JFET because of low frequency noise?

Regards,
Schmocki

 

[FvM]

Here's a chip datasheet from the original Siliconix Databook:

 

[Schmocki]

Sorry if I am sounding unpolite, but this JFET does not have a separate bulk contact. Either it does have only the bottom gate (don't know if this would be possible) or just has bottom and top gate connected together on chip.

Anyways, nice datasheet, thank you.

Regards,
Schmocki

 

[FvM]

Sorry if I am sounding unpolite, but this JFET does not have a separate bulk contact.

I see, you understand the datasheet. Of course it hasn't. No regular JFET has it, as I mentioned before. I just sent the datasheet to clarify, how the 2N4220 chip is designed. The datasheet also suggests, that the 2N4220 chip has an isolated attachment to the metal case, otherwise the gate would be connected to the case, as you find with 2N4338.

It's getting more unclear to me, what you're looking for.

 

[Schmocki]

Hi,

the 3N143 Borber mentioned has such a configuration (separate bulk connection which is connected to one pin together with the case while G, D and S have their own dedicated pins).
Only it is a MOSFET which I can not use because of too high low frequency noise.
The good low frequency noise performance is the reason why JFETs still are the preferred choice for very low noise audio amplifiers like in far distance listening devices.

If one likes to amplify ultra low frequencies he might want to omit coupling capacitors and then the bottom gate is a nice way to adjust DC bias of the amplifier circuit.

I have an old data sheet of a Philips 2N4220 where the substrate is connected just like for the 3N143, but it seems NXP has not kept the Philips transistor but rather substituted the BC245 for it.

So the search still goes on...

Regards,
Schmocki

 

[FvM]

Only it is a MOSFET which I can not use.

Only MOSFETs have regularly an electrical active bulk/substrate connection. I'm not aware of any discrete JFET that's designed with substrate connection. It should be possible to build a JFET bottom up, but I don't see a reasonable purpose for it. Would be interesting if you know about such an "irregular" discrete JFET transistor.

2N4220 isn't an original Valvo/Philips type as it's not in the 1973 data book. They have e.g. 4-pin 2N4416, but the fourth "s" pin is clearly marked as case pin. 2N4420 has been manufactured by Valvo/Philips from the mid 70th, apparently as a second source for the original Siliconix type. A same type number, second source part will clearly have an identical (sharing the chip masks) or similar (almost identical) design. It's impossible, that the original part has 3 electrodes and the second source has four...

I have seen the 1990 Philips 2N4220 datasheet at the internat, that writes "substrate" for "s". I think, it's simply a typo, the symbol shows just a case connection.

By the way, if it would be an electrical active contact, it must have at least maximum ratings, as you can find for any MOSFET's substrate pin. I keep my opinion about a "phantom device".

 

[Schmocki]

You might want to look there:

**broken link removed**

By the way, usual JFETs are built that way:

P-Substrate (for NJFET)
N-channel doping (diffusion, ion implant or epitaxy)
P-gate doping

If the substrate is not brought outside it is either connected to the top gate (symmetrical fets) or connected to the ource terminal (those fets you can not change drain and source with).

Symmetrical JFET have higher gm (2 gates in parallel) but also higher capacitance (because the bottom gate area and perimeter is larger than the top gate dimensions),.

As most substrates are connected to gate or source, it is unnecessary to specify any special ratings.

Regards
Schmocki

 

[FvM]

You might want to look there

Yes, as I said, I've seen it. I guessed the "substrate" text at the case connection is a typo. Please notice also my more detailed considerations about expectable differences between original Siliconix and second source Valvo/Philips 2N4220.

As most substrates are connected to gate or source, it is unnecessary to specify any special ratings.

With JFET, they are alway connected to the gate, I think. My statement clearly applies to the 4-pin devices, e.g. 2N4220. If the fourth pin would be a separate substrate connection, then it must have a maximum rating.

I reviewed my literature about JFET chip design and found, that you are basically right about the principle shape of the gate construction. Thank you for clarifying this point.

The same literature also shows, how both gates (bottom G2 and top G1) are usually shorted to each other, by simply extending the top gate diffussion length. So I still wonder if there will be any reference for a JFET with separate substrate electrode?

For reference, I add two pages from the said literature (in German: Das FET Kochbuch, Texas Instruments Deutschland, 1977).