Multiple block RAM modules

[dethmaShine]

I am trying to write a file from the PC to the RAM available on board.

I have verified read and write operations to a single BRAM. I have accomplished this through the UsbEpp interface.

Now I have a couple of PERL scripts running on my machine which packet the data and provide it to the UsbEpp interface through a win32 executable (C++).

All I need to do is to add more BRAM modules and make a large BRAM structure.
Also, it would be great if it is possible to switch between block RAMs at run time.

I have read almost any other tutorial but I don't understand how to use multiple block RAM modules and perform the read and write operations.

Just for the info, I am using ISE 12.1 and I code in verilog.

Any thoughts?

Thanks!

Regards

Kartik Thapar

 

[eshbonzie]

How did you implement your BRAM?

In my Case I used a generated BRAM
ISE-->new source-->IP(CORE Generator & architecture wizard)

then you choose block BRAM. A GUI will open for you and then you can configure exactly what kind of RAM, the write/read width and many other things.

I believe you dun need to create multiple BRAM if you just want to create a big BRAM structure as you can already configure it through the GUI.

You also might need to check the BRAM Blocks where u can create a block of BRAMs (check the attachment)

 

[dethmaShine]

How did you implement your BRAM?

I implemented the RAM programmatically using the following code:

module memloader(clk50,
	reset,
	ml_trans_Address,
	ml_trans_Data,
	ml_trans_WriteMe,
	ml_trans_ReadMe,
	memdout
	);
	
	defparam URAM_00.WRITE_MODE = "NO_CHANGE"; //No output unless the write operation finishes
	
	//inouts
	input clk50;
	input reset;
	input[9:0] ml_trans_Address; //10 Bit address register
	input[15:0] ml_trans_Data; //16 bit - 2*8bit data registers
	input ml_trans_WriteMe; //WriteToRAM register
	input ml_trans_ReadMe; //ReadFromRAM register
	
	output[17:0] memdout; //Output to flowhandler
	
	//nons
	reg[1:0] ml_trans_parity; //Setting parity as 0 for the time being
	wire ENABLE;
	wire WRITE_EN;
	wire SSR; //High Set/Reset used
	wire CLK_BUFG;
	
	
	//WriteToRAM/ReadFromRAM:
	assign ENABLE = ((ml_trans_WriteMe) || (ml_trans_ReadMe)) ? 1:0; //Read or Write CLOCK_ENABLE
	assign WRITE_EN = (ml_trans_WriteMe && (!ml_trans_ReadMe)) ? 1:0;

So WRITE_EN and ENABLE are based on some inputs to this particular module and then they are passed to the BRAM in the following way:

        //RAM: [0,0] - Owner
	RAMB16_S18 URAM_00(
	.DI			(ml_trans_Data), //DI contains data1data0
	.DIP			(ml_trans_parity), //parity
	.ADDR			(ml_trans_Address),
	.EN			(ENABLE),
	.WE			(WRITE_EN),
	.SSR			(SSR),
	.CLK			(clk50),
	.DO			(memdout[15:0]),
	.DOP			(memdout[17:16])); //parity

In my Case I used a generated BRAM
ISE-->new source-->IP(CORE Generator & architecture wizard)

then you choose block BRAM. A GUI will open for you and then you can configure exactly what kind of RAM, the write/read width and many other things.

I believe you dun need to create multiple BRAM if you just want to create a big BRAM structure as you can already configure it through the GUI.

I don't know how to use the GUI and I don't see the new source option.
Can you please elaborate on that?

You also might need to check the BRAM Blocks where u can create a block of BRAMs (check the attachment)

I'll check this piece of documentation. Thanks for that!

 

[dethmaShine]

Could anyone elaborate on this a bit more?

Thank you!

 

[eshbonzie]

you should be able to find the new source thing after opening ISE go to project-->new source-->IP(CORE Generator & architecture wizard). Im using ISE 11.5, maybe its a little bit different if you are using a different version but still I believe you will be able to find it some where.

after choosing the option IP(CORE Generator & architecture wizard), different available cores will appear to you to choose what ever you want. Go to "Memories & storage elements" and then "Rams & Roms" and then "Block Memory Generator" after clicking finish the block memory generator GUI will appear to you where you can setup your memory in the way you want/need.

concerning your code, I have no idea what is it..I'm still a beginner too but I faced this memory thing before so I thought sharing what I know!

 

[dethmaShine]

you should be able to find the new source thing after opening ISE go to project-->new source-->IP(CORE Generator & architecture wizard). Im using ISE 11.5, maybe its a little bit different if you are using a different version but still I believe you will be able to find it some where.

after choosing the option IP(CORE Generator & architecture wizard), different available cores will appear to you to choose what ever you want. Go to "Memories & storage elements" and then "Rams & Roms" and then "Block Memory Generator" after clicking finish the block memory generator GUI will appear to you where you can setup your memory in the way you want/need.

concerning your code, I have no idea what is it..I'm still a beginner too but I faced this memory thing before so I thought sharing what I know!

Thanks for the reply!

I do understand that. In ISE 12.1, it's under tools as Core generator.

I have read the documentation concerning Block memory generator.

This might not be a good question but I'm thinking about how much Write Width and Write Depth would I need.

So supposedly I need 5 RAMs in parallel, ie.

RAM00 RAM10 RAM20 RAM30 RAM40

and then 4 RAMs serially mapped, i.e.

RAM00
RAM01
RAM02
RAM03

This generates a 5*4 matrix or a row/column interface.

I'm using spartan 3E and 16 bits as my data width.

Can you explain me, how I calculate Write width and Write depth in this particular case or any other general case if you wish like?

And, thanks for your help!

 

[eshbonzie]

In my case, I wanted some parts of my design to be really fast and to save as much clock cycle as possible. Lets say I have a Core with 10 inputs. This core carries out some calculations on these 10 inputs. So instead of reading the 10 inputs in 10 different clock cycles (one clock cycle for each input to be read form the BRAM), I implemented 10 different Brams and I read the 10 Inputs from the 10 different BRAMs in one clock cycle (saving 9 clock cycles).

Can you explain me, how I calculate Write width and Write depth in this particular case or any other general case if you wish like?

I dun actually get the question, however the write width is the number of bits you write in one clock cycle to one memory location (one memory location size in bits) the write depth is the size of the whole memory you are implementing

lets assume you want to save 1KB of data in memory organized as 1 byte at a time (based on ur application..might be 2 bytes in one memory location):

case: 1KB of data and 1 Byte at a time
write width: 1 Byte = 8 bits..so you write 8 in the Write Width box
write depth: 1K = 1024 location..so you write 1024 in the Write Depth box


case: 1KB of data and 2 Bytes at a time
write width: 2 Bytes = 16 bits..so you write 16 in the Write Width box
write depth: 1K = 1024 location..but each location has 2 bytes..so you need 1024/2 = 512 locations..so you write 512 in the write depth box

so again I believe its all based on what do you want to implement and how do you want to access it.

One more time, please note that am not that expert..am just sharing with you what I do understand so far..some information might be wrong, but for me its working

---------- Post added at 11:22 ---------- Previous post was at 11:02 ----------

https://www.xilinx.com/support/documentation/user_guides/ug190.pdf

this might be helpfull as well..check chapter 4

 

[dethmaShine]

In my case, I wanted some parts of my design to be really fast and to save as much clock cycle as possible. Lets say I have a Core with 10 inputs. This core carries out some calculations on these 10 inputs. So instead of reading the 10 inputs in 10 different clock cycles (one clock cycle for each input to be read form the BRAM), I implemented 10 different Brams and I read the 10 Inputs from the 10 different BRAMs in one clock cycle (saving 9 clock cycles).



I dun actually get the question, however the write width is the number of bits you write in one clock cycle to one memory location (one memory location size in bits) the write depth is the size of the whole memory you are implementing

lets assume you want to save 1KB of data in memory organized as 1 byte at a time (based on ur application..might be 2 bytes in one memory location):

case: 1KB of data and 1 Byte at a time
write width: 1 Byte = 8 bits..so you write 8 in the Write Width box
write depth: 1K = 1024 location..so you write 1024 in the Write Depth box


case: 1KB of data and 2 Bytes at a time
write width: 2 Bytes = 16 bits..so you write 16 in the Write Width box
write depth: 1K = 1024 location..but each location has 2 bytes..so you need 1024/2 = 512 locations..so you write 512 in the write depth box

so again I believe its all based on what do you want to implement and how do you want to access it.

One more time, please note that am not that expert..am just sharing with you what I do understand so far..some information might be wrong, but for me its working

---------- Post added at 11:22 ---------- Previous post was at 11:02 ----------

https://www.xilinx.com/support/documentation/user_guides/ug190.pdf

this might be helpfull as well..check chapter 4

Thanks for the reply. I understood what you said. It's almost the same thing I thought.
And yes, I wouldn't mind if you were wrong. Any help is good.

Thanks!