Well Proximity effect

[PDB]

Hi,

Can any one tell me why, due to well proximity efffect, Vt of S-oriented device is more than that of D-oriented device?

I reffered following paper.

"Implications of Proximity Effects for Analog Design" by P. G. Drennan, M. L. Kniffin, D. R. Locascio.

 

[erikl]

This is due to the graded channel and - by this - the different impacts on the additional bulk (the well, in this case) control of the MOSFET (Vgb) : the S-oriented device has a higher well dopant concentration (at the source) than the D-oriented device, thus needs a higher Vt for the same Ids. I think this interrelation is quite nicely explained in the ref. paper, at the end of p.2 / begin of p.3. I'd, however, suggest to exchange the statement "the highest dopant concentration sets the threshold voltage" against "the (well) dopant concentration at the source sets the threshold voltage".

 

[PDB]

Hi,

Thank you for replying.

But, why should S-oriented device have higher vt?, as both need same voltage(Vgs) to form inversion layer.
Again as mentioned in the ref. paper, for large values of Vgs, Ids of S-oriented devices becomes greater than that of D-oriented devices.

what is the meaning of lateral electric field? and why it is formed for S-oriented devices? what about D-oriened devices? Is their any equation for Vt that mathematically proves difference in vt for these devices?

And also can you please ellaborate bit more on the first sentence of your reply.

 

[erikl]

... why should S-oriented device have higher vt?, as both need same voltage(Vgs) to form inversion layer.

This is not correct, sorry: The threshold voltage Vt of a MOSFET doesn't depend only on the gate control, but additionally on bulk control (which in this case is the well) - called the body-effect.

The body-effect is modeled by use of the bulk threshold parameter γ (gamma) [Allen/Holberg] or body-effect factor [Binkley] or body-effect coefficient [Razavi]. γ contains Nsub, the dopant concentration of the MOSFET's body (which in this case is the well). Close to the well-edge, the MOSFET's body's dopant concentration Nsub is graded (decreases away from the well-edge), hence γ decreases (with the root of Nsub) and so Vt also decreases in that direction.
See the cited books below!

Again as mentioned in the ref. paper, for large values of Vgs, Ids of S-oriented devices becomes greater than that of D-oriented devices.

Yes, and this is quite well explained in the text beginning at p.3 of the ref. paper.

what is the meaning of lateral electric field?

It (aditionally to the normal Vds) accelerates the pMOS' majority charge carriers (holes) -> higher gm

and why it is formed for S-oriented devices?

It is formed for any orientation. The electric field decreases laterally away from the well-edge (i.e. the E-field vector points into the direction of the well-edge, which means a more positive field strength at the well-edge). For S-oriented devices, this means the pMOS' majority charge carriers (holes) will be accelerated (additionally to the effect of Vds).

what about D-oriented devices?

Here, the current flow is reverse: The holes (positively charged) flowing from S to D must run against a positive drift potential (in direction of the well-edge, reversely superimposed onto the normal Vds accelerating field), thus will be decelerated -> lower gm

Is their any equation for Vt that mathematically proves difference in vt for these devices?

See here:
[Allen/Holberg] "CMOS Analog Circuit Design", Chap. 3.1 Simple MOS Large-Signal Model, equ. (3.1-3), p.74
David M. [Binkley] "Tradeoffs and Optimization in Analog CMOS Design", Chap. 3.11.1.4 Calculating gate–source voltage and drain current mismatch, equ. (3.144), p.241
Behad [Razavi] "Design of Analog CMOS Integrated Circuits", Chap. 2.3 Second-Order Effects, equ. (2.22), p.24

And also can you please elaborate bit more on the first sentence of your reply.

Guess this should be clear now from the explanation above!?

 

[PDB]

Thanks a lot...

---------- Post added at 09:04 PM ---------- Previous post was at 08:56 PM ----------

Hey I have some questions on STI.


When is deep trench isolation used? and when shallow trench isolation? Is STI also used for isolation of same devices?

 

[erikl]

Trench isolation needs - in lateral direction - about the same space as in vertical direction. Hence STI - the standard isolation method, occasionally also used between transistors of the same type - saves a lot of silicon area compared to DTI. The latter one, however, is used if either excellent isolation of single devices or cells is necessary (screening of sensible devices like sensors or input transistors from external interference, or screening of fast or power switching parts to alleviate impact on outside circuitry) - or for isolation of HV devices. Recently, more often DNW (deep n-well) is used for good noise isolation, s. the PDF below.
View attachment Impact_of_Deep_N-well_Implantation.pdf

Still better isolation is possible with the SOI process.

 

[PDB]

Hey thanks a lot...

PDB

 

[PDB]

Hi,

Have some more questions on WPE.

What is the effect on transistor performance if the well gradient is formed along the width not channel, as shown in below image?.

https://obrazki.elektroda.pl/6_1286430864.jpg

And can you please explain example 3 in p.9 in the following pdf, which is related to above question.

https://www.eigroup.org/cmc/minutes/3q06_presentations/cicc06_drennan_pres_cmc.pdf

 

[erikl]

What is the effect on transistor performance if the well gradient is formed along the width not channel, as shown in below image?
https://obrazki.elektroda.pl/6_1286430864.jpg

Here, the drain-source current flow is perpendicular to the well gradient, that means Vt resp. the channel conductivity (or Ids current density) changes over the width W .

And can you please explain example 3 in p.9 in the following pdf, which is related to above question.
https://www.eigroup.org/cmc/minutes/3q06_presentations/cicc06_drennan_pres_cmc.pdf

This results in a superimposition of both orthogonal effects of the well grading.