VHDL UART code written by Bert Cuzea of alse-fr.com

[varunmalhotra]

Hi Guys,

I am sending data via a serial cable to the Altera DE2 FPGA. but i am not getting the correct values. I think there might be a problem with the baud generator. Can some one help me with the baud gen. I have a 50 Mhz systme clock. I am trying to get the 115200 baud rate. Even a small template will do. Also
how to get to the actual statistics for the baud generator. (how the clk should be divided etc.) Apart from the this Rx code and a baud genrator. do i need any other module as well.

Thanks

This is my Rx code.

LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;


ENTITY serial_comm IS
PORT(
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
count : out std_logic_vector(3 downto 0); -- used for debugging
dout : OUT std_logic_vector (7 downto 0)
);
END serial_comm;

ARCHITECTURE simple OF serial_comm IS

type state is (idle, s0, s1, s2, s3, s4, s5, s6, s7,stop);
signal current_state, next_state : state;
signal databuffer : std_logic_vector(7 downto 0);


BEGIN

seq : process(rst,clk,rx)
begin

if rst = '0' then
dout <= "00000000";
databuffer <= "00000000";
current_state <= idle;
else
if rising_edge(clk) then
current_state <= next_state;

case current_state is
when idle =>
databuffer <= "00000000";

when s0 =>
databuffer(0) <= rx;

when s1 =>
databuffer(1) <= rx;

when s2 =>
databuffer(2) <= rx;

when s3 =>
databuffer(3) <= rx;

when s4 =>
databuffer(4) <= rx;

when s5 =>
databuffer(5) <= rx;

when s6 =>
databuffer(6) <= rx;

when s7 =>
databuffer(7) <= rx;

when stop =>
dout <= databuffer;
databuffer <= "00000000";
when others =>
dout <= "00000000";
end case;
end if;
end if;
end process;

receive: process (rst,current_state,clk,rx)
begin
case current_state is
when idle =>
if rx = '0' then
next_state <= s0;
else
next_state <= idle;
end if;
when s0 =>
next_state <= s1;
when s1 =>
next_state <= s2;
when s2 =>
next_state <= s3;
when s3 =>
next_state <= s4;
when s4 =>
next_state <= s5;
when s5 =>
next_state <= s6;
when s6 =>
next_state <= s7;
when s7 =>
next_state <= stop;
when stop =>
if rx = '0' then
next_state <= s0;
else
next_state <= idle;
end if;
when others =>
null;
end case;
end process;
-----------------------------------------------------------
-----------debug-------------------------------------------
process(rst,clk,current_state)
begin

if rst = '0' then
count <= "0000";
else
if rising_edge(clk) then
case current_state is
when idle =>
count <= "1001";
when s0 =>
count <= "0000";
when s1 =>
count <= "0001";
when s2 =>
count <= "0010";
when s3 =>
count <= "0011";
when s4 =>
count <= "0100";
when s5 =>
count <= "0101";
when s6 =>
count <= "0110";
when s7 =>
count <= "0111";
when stop =>
count <="1000";
when others =>
count <= "1111";
end case;
end if;
end if;
end process;
---------------------------------delete after wards-----------------------

END;

 

[scanman]

Rs- 232 problem

Hi varunmalhotra,

I have excellent VHDL UART code written by Bert Cuzea of alse-fr.com. Nice simple code and I have been using 115200 baud to send data from FPGA to PC. No problems works great. Let me know and I will post UART code here.

Cheers,
Scanman

 

[varunmalhotra]

Re: Rs- 232 problem

Thanks Scanman

that would be great..please post the code.

thanks alot for the prompt reply

 

[scanman]

Re: Rs- 232 problem

Varunmalhotra,

Here is the code. Thanks to Bert Cuzea of alse-fr.com for sharing his awesome UART with us.

Cheers,
Scanman

 

[varunmalhotra]

Rs- 232 problem

Hey scanman,

i dont see the code. may be it dodnt attach with the post.

Please have a look

Thanks

Added after 2 minutes:


Sorry about that, i see it now.

Thanks

 

[pssiko@yahoo.com]

master i have open the file, and open it using Xilinx ISE 8.2i after that ,when trying to assign package pin i am blank to what should be filled here(the picture i insert)

 

[scanman]

Here is a state machine for transmitting bytes from FPGA to PC via RS-232.

 

[sachinkhati]

Re: Rs- 232 problem

Hey scanman,

i dont see the code. may be it dodnt attach with the post.

Please have a look

Thanks

Added after 2 minutes:


Sorry about that, i see it now.

Thanks

@ varun, @scanman

please tell me how did you get the zip file . i am not able to see it

oh i see it now

for others who might have the same problem
u must be logged in to see the .zip files

 

[sachinkhati]

Re: Rs- 232 problem

@scanman

Hi can you send me the detailed documentation of the uart ip



@varun

did you verified it with a board . share you experience

i am trying to interface the uart ip with my vhdl module so that it can communicate with my spartan 6 fpga board.
seniors pour in some thoughts

 

[sachinkhati]

Re: Rs- 232 problem

@scanman


can you share the other modules like applic.vhd and uarts.vhd

 

[dsl2640free]

I found excellent VHDL UART code written by Bert Cuzea of alse-fr.com.
full version:
direct links on french sites:

**broken link removed**

**broken link removed**
:roll: