16-bit CD-Audio successive approximation ADC ?

[skjsun]

is this actually doable in 0.35 um or 0.5 um CMOS nowadays without calibration or trimming ? i do not want to do a sigma-delta ADC for this "threshold" resolution (16 bits, cause it's high, but not too high to keep successive approximation out of choice), can anyone give me suggestions ?

 

[Vamsi Mocherla]

Hey try and design using an integrating architecture. I would suggest a dual slope or a quad slope architecture in order to achieve the required resolution. There are designs using integrating architecture and achieving a 16 bit resolution. Only you should be able to achieve that speed and good component matching. And importantly, the speed is a critereon. I am not sure whether Integrating ADCs achieve such high speeds.

But mostly people prefer sigma delta for these kind of resolutions and

 

[skjsun]

thanks very much, but if you use dual slope, for the case of 9k samples/second, you must have a clock frequency of about 590 MHz (2^16*9000, because you must count down 2^16=65536 times to decide which level the sample is in), which is not quite feasible, is it ?

 

[eldo]

For SAR ADC, 16 bit is difficult. You need a 16 bit DAC first, which is already difficult without calibration or trimming.

 

[uladz55]

It's impossible to get 16 bit SAR ADC without calibration.
And it's almost impossible to get even 12-bit SAR ADC w/o calibration.

You can check for ex. Analog Devices or MAXIM ADC spec:
AD7440 - 10 bit, AD7440A - 12 bit.
AD7621, MAX195 - 16 bit

Best regards

 

[maxwellequ]

12 bit SAR is still feasible. Significantly more than that, you need to calibrate the internal DAC.

 

[Beardsh]

Before, I designed Sigma-Delta ADC. Sigma-Delta is a better choice to achieve 16-bit (SNR-->96dB) performance. And Sigma-Delta ADC is much easier than other types. Maybe Sigma-Delta ADC is a possibility for you.

 

[mists]

although i don't think that sigma-delta ADC is easy, but it is a good choice to achieve 16-bit accuracy low speed ADC.

 

[crossbow_123]

is this actually doable in 0.35 um or 0.5 um CMOS nowadays without calibration or trimming ? i do not want to do a sigma-delta ADC for this "threshold" resolution (16 bits, cause it's high, but not too high to keep successive approximation out of choice), can anyone give me suggestions ?

hi,sar adc is suitable for 10 bit, without trimming or calibration, it is hard to achieve 16bit. sdm adc is your choise.

 

[viks_iisc]

I will rather say 16 bit SAR ADC is doable provided the MSPS is not very high !

Go for Time Interleaved SAR ADCs !! 2 SAR ADCs 8 bit each working in time-interleaved fashion will do ur job !!

Added after 1 minutes:

If its Audio, its very possible !!