15nm technology how to configure

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santrasantanu

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Hi everyone,
I want to design some basic gates like 2 inputs AND, OR, NAND etc. using Nangate 15 nm PDK technology. but I can not configure NanGate 15nm PDK technology with Virtuoso-6.1.5 . I do not find any help for configuration from the internet. Please let me know from where I can get some help otherwise please inform me the steps.

Thanks in advance!
Santanu Santra
 

Try to find appropriate layout templates of these gates in larger processes, understand their layout and arrangement, then shrink the W/L ratios of their transistors suitably to your process size.

Eventually adapt the W/L ratios of the PMOSFETs to the µp/µn (mobility) ratio of your process. For optimization use simulation analysis to achieve the required propagation delay and/or symmetrical rise-/fall-times.
 


Are you sure this process is %100 compatible with IC 6.1.5 ? I mean configuration of this PDK should be explained somehow in its help dir or somewhere else..
If it's so, loading libinit.il ( or similar ) skill starup file should load all necessary settings into Virtuoso environment.
 

Hi erikl,
I know how to configure these basic gates using 180nm and 45nm pdk technology, but for 15 nm pdk technology I did not find any help.
If you know how to configure, please help me.
thank you.
Santanu Santra
 

Why don't you use the same configuration as, e.g., in the 45nm std. lib? Just define your new cell height, the power supply rails, the i/o connectivity positions, then scale down and optimize the W/L ratios as I told you above. L=Lmin of the process.

If you have a concrete question, ask again!
 

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