Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to size the dummy transistor

Status
Not open for further replies.

cdz

Junior Member level 2
Junior Member level 2
Joined
Mar 21, 2008
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,434
Hi Everyone,

For the dummy size, should I use the minimum length of the technology or use the same length of the transistors that I will put the dummy beside? For example, in the current mirror in 90nm, the transistor is 3/0.4(W/L), when I put the dummy beside this transistor, the size of dummy should be 3/0.4 or 3/0.10. Thanks

CDZ
 

safwatonline said:
i usually use the same size

Thanks for reply. Why? Because I think if I use the minimum length for the dummy, the size of the cell will be smaller than that use the same size. Then when you connect these cells, it may use long wires to connect them, therefore the parasitic capacitance will increase.

CDZ
 

I believe only the edge of the dummy is important, so the minimum size transistor will do (and I have not seen any problems so far).
 

you can go wiht the same size or minimum depending on the difference.... minimum lenght is usually prefered ... if the lenght of active device is big.. otherwise go for same length....

Added after 3 minutes:

cdz said:
safwatonline said:
i usually use the same size

Thanks for reply. Why? Because I think if I use the minimum length for the dummy, the size of the cell will be smaller than that use the same size. Then when you connect these cells, it may use long wires to connect them, therefore the parasitic capacitance will increase.

CDZ

I assume we are talking abt analog where the devices are placed manually... so i dont understand your point of long wires.... you can place the cells near to reduce interconnect parasitics......

Moreover smaller cells willl reduce teh size of the layout.. please correct me if i m wrong
 

Minimum length is OK. But make sure that D/S contact to poly spacing remains same as that in the actual device and also ensure that same poly to poly distance is maintained as the spacing between the actual devices.
Regards,
Diensh
 

There is always this boring Answer: It depends.

Okay, to start off the question was not clear..

how to size the dummy transistor ?? depends on the question What is the functionality of the the matching transistors you are placing dummies for ?

this plays huge role in dummy size..

why: because you are basically placing dummy to protect the edges and avoid the mismatches in gate length due to process.. right.. but when these transistors are already in the silicon why not think smart. may be, we can use them in case if you have current ratio problems with the mirrors.

so if you are placing dummies for the current mirrors ... then you better place same size dummies and connect the gates of these dummies to the gate of the mirrors (obviously the mirrors have same gate connection , and also its a voltage node so a little cap on that node is never going to hurt) and short the drain and source to power or ground based on whether its n or p But just make sure the transistor is off. so,in future would you need them, all you do is change one metal mask (which is a lot cheaper than touching the actual silicon) to change the drain connection.as the source remember you already connected to ground.

But if you are working at RF, Its a whole new story. Here the minimum the dummy length less cap hence better functionality.

So this is what i know, have been using, has been working so far.

Thanks for your time.
Venu :D
 

i can,t agree with you more. always keep in mind that you may take the most of the dummy for those non-rf devices
 

jnvenugopal said:
There is always this boring Answer: It depends.

Okay, to start off the question was not clear..

how to size the dummy transistor ?? depends on the question What is the functionality of the the matching transistors you are placing dummies for ?

this plays huge role in dummy size..

why: because you are basically placing dummy to protect the edges and avoid the mismatches in gate length due to process.. right.. but when these transistors are already in the silicon why not think smart. may be, we can use them in case if you have current ratio problems with the mirrors.

so if you are placing dummies for the current mirrors ... then you better place same size dummies and connect the gates of these dummies to the gate of the mirrors (obviously the mirrors have same gate connection , and also its a voltage node so a little cap on that node is never going to hurt) and short the drain and source to power or ground based on whether its n or p But just make sure the transistor is off. so,in future would you need them, all you do is change one metal mask (which is a lot cheaper than touching the actual silicon) to change the drain connection.as the source remember you already connected to ground.

But if you are working at RF, Its a whole new story. Here the minimum the dummy length less cap hence better functionality.

So this is what i know, have been using, has been working so far.

Thanks for your time.
Venu :D
.. In the current mirror portion i guess you are talking abt spare transistor. I beleive if you connect dummies in the way you are sugestin it will lead to more gate loadijng.. and effectively it will work as cap at teh gate.. your dummy transistors i m talking about....

Please elaborate on theis point.

Added after 1 minutes:

and i n RF i dont understand how your dummy gate willl add parasitics.....
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top