which tool or program can change Spice to verilog netlist

[xiantongma]

spice to verilog perl

i am work in digital group project , need change Spice to verilog netlist , so that i can simulate only need digital simulator tool , like vcs , modsim
which tool or program can change Spice to verilog netlist

thank you

 

[paulki]

spice2verilog

Hi,
Check this link :
**broken link removed**

I dont think any Verilog Netlist is generated with any tools out of SPICE Netlist.
And the tool cost also would be very much high. Better to procure one AMS license from cadence or Synopsys for Mixed Signal Simulations (AMS license can do Analog-Digital Mixed Signal Simulations, rather than converting Spice to erilog)

-Paul

 

[tariq786]

cdl to verilog script

Usually people do it the other way. That is they generate spice netlist from verilog.

But what you said is possible using perl script. For ease of design, make sure you specify spice netlist in terms of sub circuits. For example, consider the following hspice netlist


X0 n1 n2 dout_4 nand2


X1 n3 n4 n5 dout_3 nand3


X2 n6 n7 n8 dout_2 nand3


X3 n9 n10 dout_1 nand2


X4 n12 n13 n11 nor2


X5 n11 n15 n14 nor2


.subckt nand2 n1 n2 dout
m0 dout n1 vdd vdd pmos l=250e-9 w=500e-9
m1 dout n2 vdd vdd pmos l=250e-9 w=500e-9
m2 dout n2 n_i 0 nmos l=250e-9 w=500e-9
m3 n_i n1 0 0 nmos l=250e-9 w=500e-9
.ends nand2



.subckt nor2 n1 n2 dout
X789 n1 n1_inv inv
X790 n2 n2_inv inv
X791 n1_inv n2_inv dout and2
.ends nor2




A spice file like this is easy to convert into gate level verilog using Perl script since you just have to write the lines in a different format e.g.

X5 n11 n15 n14 nor2 can be written in gate level verilog as

nor uinst_X5 (n11,n15,n14)


Hope it helps.

 

[itsmeteja]

spice to verilog

Magma design automation has some knight converters.One of the utility in the knight converters is spice2verilog using which you can convert the spice netlist to the verilog.But the license costs a lot..

 

[xiantongma]

spice .subckt m0

perl script ideal is good , i am is writting perl , chang analog .cdl change into verilog