Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Pre-layout simulation is the one you use to check if your gate-level netlist (right after Synthesis) is functionally correct.but the post layout simulation "no longer in use" was to check that the gate-level netlist is still functionally equivalent the pre-layout one because you have added the clock tree, buffers,scan chains etc..
In today's physical design flow, designers use functional verification as a way to check that the circuit function is right after synthesis.it uses mathematical formulations rather that dynamic simulation.it is much faster and more mature now.
they also use the STA "statical timing analysis" to compensate the fact that functional verification can't check timing of the circuit....
Pre-layout simulation is the one you use to check if your gate-level netlist (right after Synthesis) is functionally correct.but the post layout simulation "no longer in use" was to check that the gate-level netlist is still functionally equivalent the pre-layout one because you have added the clock tree, buffers,scan chains etc..
In today's physical design flow, designers use functional verification as a way to check that the circuit function is right after synthesis.it uses mathematical formulations rather that dynamic simulation.it is much faster and more mature now.
they also use the STA "statical timing analysis" to compensate the fact that functional verification can't check timing of the circuit....
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
