End cap, well tap cell definition and spare cell usage

[cafukarfoo]

well tap cells

Hello everyone,

Can you help to give me a bit of information about End cap and well tap?
For example,
1. What is the usage of this 2 type of cell?
2. Is it a must for every ASIC chip?

As for spare cell,
Normally what is the kind of cell added for the spare module?.

Thanks in advance for your help.

 

[hiral.kotak]

end cap cells

Hi,

Actually the sparecells that you need to insert in your design will come from the top level designer. But if not then you can insert sparecells equal to 2% of your total design cells. And regarding to the
sparecell list, you can include the cells as per the max number of the types used in your design.
You should use, buffers and inverters, flipflops, muxes, and universal gates in a sufficient amount, so that any functionality can be formed with that and if any timing violations then you can use either buffers or inverters.
Endcaps are placed at the end of cellrows and handle end-of-row well tie-off requirements.
The library does not have well or substrate ties inside the cells. You are required to tie the NWELLS to Vdd and
the substrate to Vss before place-and-route using the FILLTIE cell.
It may help you.

Thanks..

HAK..

 

[cafukarfoo]

end cap cell

Hi hiral.kotak,

Can you explain this more?

Endcaps are placed at the end of cellrows and handle end-of-row well tie-off requirements.

Thanks.

 

[hiral.kotak]

tap cell

Hi,

Endcaps are used to connect power and ground rails across an area and are also used to ensure gaps do not occur between well or implant layers which could cause design rule violations.

Thanks..

HAK..