What are the benefits of a negative set up time?

[ASIC_intl]

Set-up time can be negative theoretically? Is there anyone who has seen the set up time to be negative in any library?

If so please let us know the benefits of a negative set up time. What is the reason that the set up time is defined negative in library?

 

[Riveywood]

negative setup

Negative set-up time just means that it is permissible for the signal to arrive after the clock edge and there is usually a corresponding increase in hold time.

It can sometimes be seen in situations where there the clock path has a much longer delay than the signal path (between the point where the setup hold time is measured and the point where the signal is actually sampled).

 

[ASIC_intl]

negative setup

how can there be increase in hold time for negative set up time?

Are negative hold time is deliberately made? Are they accidentally caused? What are the benefits of negative setup time?

Added after 47 minutes:

Are negative setup time is deliberately made? Are they accidentally caused?

 

[Nir Dahan]

negative setup time site:www.edaboard.com

how can there be increase in hold time for negative set up time?

just imagine a flop with some buffers at the clock input that delay the clock signal. now wrap all in a nice wrapper and call it a flop. as mentioned above this "new" flop can have negative setup but its hold will increase.

It is hard to gain everywhere in life...

ND.

https://asicdigitaldesign.wordpress.com/

 

[ASIC_intl]

advantage of having negative setup time

How can u get some buffers in clock path if you design your flip flop without those buffers and send them for fabrication. Again after fabrication these flops are charecterized with their set-up, hold etc. and put it into the .lib file.

 

[Nir Dahan]

что такое negative setup time

you asked for A way - and I tried to give an example of A possible way this can be done.
it is just illustrative example, I don't say you should go and design like this now


ND.

https://asicdigitaldesign.wordpress.com/

 

[jarodz]

uptime negative

Hi ASIC_intl,

When the clock signal transation time is too slow and the data signal transation time is too quick, the setup time will be negative. And the setup time + hold time >= 0. The total of setup time and hold can be view as the data must be stable period. If the setup time decrease, the hold time will increase. You can image that the timing window is just shifted.

Sincerely,
Jarod