Dual edge counter in VHDL?

[Mehdi1357]

vhdl dual edge

Hi everbody
How can write a process in VHDL for dual edge counter(counter increases its value each time a rising or falling edge occurs)?
thanks

 

[avimit]

vhdl rising edge

You will have to have 2 counters, one which work on -ive edge, and the other which work on +ive edge. Each counter will increment the count by 2. One will start with 0 the other will start with 1. You can then multiplx the o/p value as desired.
kr,
Avi

 

[Mehdi1357]

vhdl double edge

Hi
I appreciate your answer.is there a more simple solution for processing of both edges of a input signal in a PROCESS block.please write VHDL code.
best regards.

 

[avimit]

edgecounter

No there is no simpler answer or a method to do this in a single procedural code, which will be synthesizeable
Kr,
Avi

 

[FvM]

verilog dual edge flip flop

There have been various threads on the same topic, e. g.

 

[mmarco76]

vhdl edge

Your question is very simple.
If the signal you wanna count is a clock simply your code will be something like this:

process(reset, clk).
begin
if reset = '1' then
counter <= (others =>'0');
elsif clk'event then
counter <= counter +1;
end if;
end process;

If you wanna count a signal that is not a clock, but it's clocked by your clock under certain condition (signal last at least 3 clk before changing state) you can detect the 2 front and then increase your counter by them.

Hoping to help you with this simple answer.
If need more help ask with more details.

 

[lucbra]

vhdl rising and falling clock edge

Yes but this code is NOT synthesisable. There is no hardware FF that supports this.

 

[karikalan_t79]

dual edge counter

tool will tell this is impoosible to attend a ff in the design and result in error

 

[Mehdi1357]

edge counter vhdl

Your question is very simple.
If the signal you wanna count is a clock simply your code will be something like this:

process(reset, clk).
begin
if reset = '1' then
counter <= (others =>'0');
elsif clk'event then
counter <= counter +1;
end if;
end process;

I appreciate you for your answer , but your code isn't synthesizeble in ISE version 10.1 (related to Xilinx's productions).
this problem will solve by using two processes , one for rising edge and another for falling edge then we must mix these results together.
best regards.

 

[Core1]

vhdl edge counter

Hi everbody
How can write a process in VHDL for dual edge counter(counter increases its value each time a rising or falling edge occurs)?
thanks

it's not the synthesizer, it's the target
look at this simple code: (sorry, I'm a verilog guy)

always @(posedge clk or negedge clk)
x = x + 1;

It is synthesizable and it does work in some CPLD's like XC2Sxx (Xilinx)
The target you point the synthesizer to must have dual-edge support.

 

[Nir Dahan]

fpga dual edge ff

one could create a dual edge flop as described here:
https://asicdigitaldesign.wordpress.com/2007/07/31/the-double-edge-flip-flop/
or here:
https://asicdigitaldesign.wordpress.com/2008/09/22/another-look-at-the-dual-edge-flip-flop/
ND.
https://asicdigitaldesign.wordpress.com

 

[alexan_e]

Re: fpga dual edge ff

Hi
This is and old thread but this update may help someone.
I have used only one counter that increments by 2 at falling edge of the clk.
When the clock=1 the output is the counter value OR 1 , if not then the output is the counter value.
I assume that this is driven by a 0-1-0-1-0 clock if not you could also check for clock=0.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dual_edge_counter is
  port ( clk				:in std_logic;
	  output			:out std_logic_vector(7 downto 0) );
		  
end dual_edge_counter;

architecture Structural of dual_edge_counter is
signal counter :std_logic_vector(7 downto 0):=(others=>'0');
begin
 
process (clk)
 begin	
	if (clk'event and clk='0') then		
		counter<=counter+2;
	end if;	
		
end process;

output <= counter when clk='0'
else (counter or "00000001");

end Structural;

simulation result
https://obrazki.elektroda.pl/98_1289953468.gif

I have included an attachment with the code plus test-bench and simulation result

Alex

 

[boopy]

Re: fpga dual edge ff

Hi.
I used a flag:
variable ClkFlag : std_logic := '0';

My process only includes the clock in its sensitivity list:
process (CLK)

Then, everytime the process is run the flag is toggled:
ClkFlag := not ClkFlag;

The code for rising and falling is selected according to the flag
if ClkFlag = '0' then
ClkFlag := not ClkFlag;
....
else
ClkFlag := not ClkFlag;
.....
end if;

 

[FvM]

"Dual edge counter" sounds nice and of course, it looks fine in functional simulation. Practically, your just supplementing the clock signal as LSB to a binary counter. But the counter output is assembled asynchronously, the counter bits are delayed related to the clock signal. Without sampling the result at the right time it won't be valid. So there may be doubts, if the solution actually serves a purpose.