How to plot the gain of a CMOS inverter?

[cfreng2]

Hello all! Does anyone know how to plot the gain of a CMOS inverter? How can we get the gain of a CMOS inverter? And how can we plot it in winspice?... Please help me.

 

[LvW]

cmos inverter gain

I am not familiar with WINSPICE, however, in general there are two alternatives - depending on your desire.

1.) DC gain: Perform a dc-sweep and plot Vout vs. Vin. The slope of the transfer curve gives you the dc gain for each bias point of this function.

2.) AC gain: If you are interested in the frequency response, choose a suitable bias point and perform an ac analysis. The you can plot Vout(rms) vs. Vin(rms) which gives you the absolute gain as a function of frequency.

 

[cfreng2]

gain of inverter

thanks for your help!

 

[Audioguru]

cmos inverter frequency response analysis

RCA plotted the voltage gain of a Cmos inverter a long time ago.
The gain depends on the supply voltage and the frequency.
But I cannot attach the graph and I don't know why not.

Added after 4 hours 3 minutes:

What a nuisance!
I can't attach the graph because it has already been attached to this other thread:

 

[yangyang10182]

Re: cmos inverter gain

I am not familiar with WINSPICE, however, in general there are two alternatives - depending on your desire.

1.) DC gain: Perform a dc-sweep and plot Vout vs. Vin. The slope of the transfer curve gives you the dc gain for each bias point of this function.

2.) AC gain: If you are interested in the frequency response, choose a suitable bias point and perform an ac analysis. The you can plot Vout(rms) vs. Vin(rms) which gives you the absolute gain as a function of frequency.

Hello LvW,

I want to use Cadence to simulate the DC gain and gain bandwidth of a CMOS inverter. I saw your post here and thank you for your information. I did the simulation for DC gain in Cadence and plotted Vout vs. Vin. But I could not be able to tell the slope of the curve. Could you please help me to do this? In the simulation, the supply voltage is 3V. I swept the Vin from 0V to 3V and got the output. I attach the plot here. Could you please have a look at it and tell me what's wrong with it? Thanks in advance.

 

[Audioguru]

RCA posted the AC gain and bandwidth for Cmos inverters about 36 years ago. It is affected by the supply voltage. It is here:

 

[yangyang10182]

RCA posted the AC gain and bandwidth for Cmos inverters about 36 years ago. It is affected by the supply voltage. It is here:

Thanks, Audioguru. Do I need to use the exactly the same resistors to do the simulation? Does the resistance value affect the gain?

 

[Audioguru]

If the inverters have a very high open-loop gain then the resistors set the gain to 10,000 (80dB). But the graph shows the max gain is only about 500 (54dB) when the supply is only 3V and there is no load.
If the 1k input resistor has its value increased or the 10M feedback resistor has its value reduced then the gain will be less.

 

[LvW]

Re: cmos inverter gain

Hello LvW,
I want to use Cadence to simulate the DC gain and gain bandwidth of a CMOS inverter. I saw your post here and thank you for your information. I did the simulation for DC gain in Cadence and plotted Vout vs. Vin. But I could not be able to tell the slope of the curve. Could you please help me to do this? In the simulation, the supply voltage is 3V. I swept the Vin from 0V to 3V and got the output. I attach the plot here. Could you please have a look at it and tell me what's wrong with it? Thanks in advance.

At first, increase the resolution during simulation (more points to be calculated). Your diagram shows to many "edges" and should be "smoother". Then, it should not be a problem to detrmine the slope around the linear portion of the transfer curve.
This gives you the open-loop gain.

After providing some negative feedback (as shown in the provided circuit diagram) the gain will be reduced - depending on the ratio of both transistors (correction: resistors) (as mentioned by audioguru already). This case is similar to an opamp in inverting mode.
However, the verification/calculation of the gain value depends on the (relatively large) output resistance of the CMOS stage. This is in contrast to the inverting opamp circuit.

---------- Post added at 21:39 ---------- Previous post was at 21:07 ----------

I forgot to mention that it is necessary to use an input coupling capacitor because the operating point needs dc unity gain (100% dc feedback) - in case of single supply. Otherwise the circuit cannot work as desired.

 

[Audioguru]

Your simulation program shows a negative image that is very hard to see. I made it into a positive image and increased the contrast.
The Sim program does not have a correct model of a Cmos logic inverter so its gain is far too low.

 

[yangyang10182]

Your simulation program shows a negative image that is very hard to see. I made it into a positive image and increased the contrast.
The Sim program does not have a correct model of a Cmos logic inverter so its gain is far too low.

Audioguru, Thank you very much for your reply.

The plot I got here is for the DC gain. The graph from DRC is for AC gain? I guess. And the plot here I did not use enough points that's why the gain is low. Attached is the new plot I got.

 

[yangyang10182]

Re: cmos inverter gain

At first, increase the resolution during simulation (more points to be calculated). Your diagram shows to many "edges" and should be "smoother". Then, it should not be a problem to detrmine the slope around the linear portion of the transfer curve.
This gives you the open-loop gain.

After providing some negative feedback (as shown in the provided circuit diagram) the gain will be reduced - depending on the ratio of both transistors (as mentioned by audioguru already). This case is similar to an opamp in inverting mode.
However, the verification/calculation of the gain value depends on the (relatively large) output resistance of the CMOS stage. This is in contrast to the inverting opamp circuit.

---------- Post added at 21:39 ---------- Previous post was at 21:07 ----------

I forgot to mention that it is necessary to use an input coupling capacitor because the operating point needs dc unity gain (100% dc feedback) - in case of single supply. Otherwise the circuit cannot work as desired.

LvW, thanks very much for your explanation and suggestions. For the DC gain , I use the DC sweep simulation in cadence. Is it right? And for the AC gain, I can use the circuit as Audioguru mentioned above and do the AC simulation or the stability simulation?

 

[Audioguru]

The gain of the new simulation is still far too low. If the gain is correct at 500 then you will not be able to see the very small input swing on the graph.

 

[LvW]

May be that the gain is to low (as audioguru says) - however, audiogurus calculation is not correct as he is evaluating a part of the transfer characteristic that contains nonlinearities.
But it is possible to simulate the open-loop gain using a real small signal method: ac analysis.
For this purpose, use a very large feedback resistor (1...10 megohms) between output and input only (without the input resistor), but instead connect the ac voltage source via a large coupling capacitor.
By the way, I don't expext stability problems with such a circuit.

 

[FvM]

The gain of the new simulation is still far too low.

I don't think so. Ro*gm around 20 to 30 is a reasoanable number for transistors in recent standard technlogies. Applying the values from a CD4000 inverter isn't necessarily correct.

 

[jony130]

Simply use simulation math to show you the gain. The derivative of the transfer function is the voltage gain.