Help me with gate level simulation using VCS

[balasub]

Hi,
I am new to gate level sim..
I got a netlist and a sdf file post Place & Route...

Now i am trying to simulate the same using the same verification env. used for normal RTL simulation.

I am using VCS.

I am getting some fails rit at the beginning of my simulation.

What are various things i need to keep an eye on in debugging this.

Please help!

Thanks!

 

[skyfaye]

gate sim debug help

One of the things that you will most likely encountered in gate sim with timing is synchronizers failing timing checks, that is if you have it enabled. Instead of changing your stimulus to avoid this, what's typically done is either disable timing checks on those synchronizers or hack the sdf file and zeroed out the timing check numbers (setup/hold/etc. values), which in effect is like disable timing checks on those instances. VCS support disabling timing checks on a per instance basis or for the entirely. If you have Verdi, then you can easily trace the X's back to it's source and find these synchronizers or just ask the designers.

- Hung

 

[pintuinvlsi]

gate sim with -ve delays

You have to take care of many things during gate sims run.

1. If you are using same RTL simulation verification enviroment for gate sims then you have to put some delay while driving the inputs as here setup and hold come in picture.

2. You have to initialize all uninitialized fllops.

3. Disable the timing checks of all sync flops.

4. Initialize all memory and registers of DUT just before DUT comes out of reset.

 

[skyfaye]

Re: gate level sim help

You have to take care of many things during gate sims run.

1. If you are using same RTL simulation verification enviroment for gate sims then you have to put some delay while driving the inputs as here setup and hold come in picture.

Why? The same exact stimulus should work in both RTL and gate sim (with or without timing). If you're driving the stimulus onto a synchronous I/F, there's no way you can violate setup/hold time. If you're driving the stimulus onto an asynchronous I/F, then you already take care of that problem by disabling the timing checks on those synchronizers (step 3).

2. You have to initialize all uninitialized fllops.

Why? Assuming all the necessary initialization of the chip is done correctly in the RTL simulation, you shouldn't have to do anything for the gate sim. Who cares if you have some uninitialized fllops in the netlist if they don't cause any problems.

3. Disable the timing checks of all sync flops.

Agree.

4. Initialize all memory and registers of DUT just before DUT comes out of reset.

This step doesn't even make sense. How can you initialize memories and registers when the chip is in reset? By using backdoor method? Again, the initialization routine that you use for the RTL should work for your gate sim.

Please see my comment above.
So what I'm trying to say is this. The only thing you need to do for gate sim (with timing) is disable timing checks on your synchronizers, unless you want to change your stimulus (NOOOOOOO).

- Hung

 

[ljxpjpjljx]

Re: gate level sim help

yes, you run the GLS should include some items: inilize some register, inilize some memory and close some timing check for corss-clock domain signals.

 

[balasub]

Re: gate level sim help

hi,
once i start asserting/deasserting the reset i get a few timing violations .
Should i consider this at all as valid violations?

Also after these messages ,the devsel doesn't get asserted by the dut.Here pci interface is used.

I really don't know how to go further with this.
Meaning what are the various ways to debug issues in GLS.

Thanks!

 

[cihchenlin]

gate level sim help

why Disable the timing checks of all sync flops?

asyn?

 

[balasub]

Re: gate level sim help

hi,
My testbench is driving a signal Y in the DUT.

Now i see that at one instance the signal Y comes a little earlier than the posedge of the clk hence when we expect this signal to be a 0 it is a 1.
To me it looks like the clk is delayed more that the signal Y.

Or Y has to be delayed to keep in sync with the clk delay.

How can this be handled.?Are such issue quite common in GLS and how can it be fixed?
Thanks!

 

[skyfaye]

Re: gate level sim help

why Disable the timing checks of all sync flops?

asyn?

If you don't, then you might violate setup/hold/etc. checks and get X's as outputs on these sync flops. Since sync flops are used only in async I/F, you can't guarantee your stimulus will always meet the setup/hold/etc. times. So rather than making your stimulus to avoid violating the timing checks (probably very difficult and not worth the effort), you can just disable the timing checks on those sync flops and you will never get a timing violation. Of course, you don't get X's in the silicon but only in simulation.

- Hung

 

[balasub]

Re: gate level sim help

hi,
i sucessfully completed one GLS.But that was a basic one looks like after all the debug.

Now i have one more in hand.
In here the design uses a vendor IP too.
So the netlist has the vendor IP incorporated.

Now my question is :

say if we use defines in our simulation (RTL) how will this get reflected in the netlist(for Gate Level Sim)

Say for example we have a define to select only 1 of the available 8 ports in our RTL sim,how will this be taken care in netlist??

Looking for urgent answers please...

The difficult part is all the defines used are corresponding to the IP.

Thanks!

 

[jonyRoyal]

Re: gate level sim help

Verdi can help you to debug it within 2-10 min
you can trace back & you can find source of the bug/value(Xvalue) for particular signal

 

[balasub]

Re: gate level sim help

what is verdi?

i have no knowledge of it....

 

[jonyRoyal]

Re: gate level sim help

Verdi is debugging tool (Industry standard)......
you can get more detalis on..
www.novas.com