`timescale usage in Verilog?

[want2LearnVlsi]

verilog timescale directive

Hi,

Why the directive `timescale should be used?
Suppose if we donot use the 'timescale directive, and mention the delays like #10, etc, how the simlator will consider it?

KSSR

 

[deepu_s_s]

timescale directive in verilog

Hi
`timescale directive is not used to produce delays like #10

Added after 4 minutes:

let us consider

`timescale 1ns/1ps

reg set;
parameter d = 1.55
initial
begin
#d set = 0;
#d set = l;
end
endmodule


The `timescale tells the system to use 1 ns for all reporting and internally use 1 ps
for resolution of time in this part of design. Thus, the value for parameter d is scaled
to a delay of 1.55 ns. Had we used timescale directive `timescale 10ns/1ns, 1.55
would mean 15.5 or 16 ns. The first part of `time-scale gives the time-units and the
second part gives the time-precision.

 

[100ml]

timescale directive verilog

so by the `timescale directive can i generate a clock of 1Hz ???

 

[pramodm]

timescale verilog

`timescale is compiler directive using this we con not generate any signal it is used to indicate the time scale and its resolution

example

if we specify `timescale 1ns/10ps

it means we specifing the dealy values used in our discreption as in ns and the simulation resolution of 10ps