Bi-phase mark data & clock recovery in FPGA

[TurboPC]

biphase clock recovery

Hi,

I have a 24MHz bi-phase mark signal and I want to recover the data and clock using a Xilinx or Altera FPGA. I prefer not to use DLL or PLL inside a FPGA since there may be too much jitter on the signal and fpga DLLs are sensible to jitter.

I am ready to use an external 24MHx VCXO and to lock to the bi-phase mark signal, but I am not quite sure how to do it.

1) I am familiar with VCXOs and PLLs but with a bi-pahse mark signal, I don't see how to get a stable edge to send to my phase comparator.

2) What's the best way to properly extract the data with the recovered clock?

Any reference design? Ideas? Links?

Thanks!

TurboPC

 

[robotman]

clock recovery fpga

Try looking at X$l$inx

XAPP 224
XAPP 250

I think this will help you a little

robotman

 

[TurboPC]

biphase mark clock recovery

I looked at the appnotes and tried something. I can't recover the clock properly. The DLL are useless until you have a stable clock.

I have a 24 MHz VCXO and I try to lock on a 24MHz bi-phase mark signal.

The first thing I need to do is to lock the vcxo to the signal. Since it is a bi-phase mark signal, I don't know how to use it with a phase comparator (using a tristate driver to the vcxo).

Once it is locked, it is very easy to extract the data using the vcxo and the DLLs by using the 0, 90, 180 and 270 degrees clock outputs.

Anybody has tried that successfully?

 

[robotman]

vcxo fpga

What is your control mechanism for the external vcxo? Integrator? DAC? other?

What is the clock rate of the data? Is is the same as the vcxo?

Can you attach a partial schematic?

robotman

 

[TurboPC]

edge detector xlinxs

Yes: the data and vcxo are both at the same frequency.

The phase comparator is a "first edge" detector that controls a "pull-high" or "pull-low" tristate buffer depending if the vcxo edge or the bi-phase mark edge comes first. The high/low signal goes to the vcxo through a low pass filter. When properly locked the tristate buffer is nearly in tristate and the low pass filter acts as a "sample and hold".

Not clear, right?

Let's try another approach...

The problem with a bi-phase mark data is that you never know when there will be a rising edge that you can use to compare with the vcxo clock.

Then, how to lock the vcxo to the data?

At this point, I'll accept any idea...

 

[robotman]

dpll recovers the clock

A couple of things come to mind.

Most circuits that I have seen that perform this function use a much higher frequency to oversample the input and make decisions. This allows for better jitter control. A digital filter can be used to estimate the adjustments to the vcxo.

Do you have an estimated pull range of the vcxo? If it is within the range of a DCM or DLL would you consider using it as a frequency multiplier?

Let me do a little more digging. I will try to figure out something different.

robotman

 

[TurboPC]

fpga oversampling clock recovery

Thanks Robotman for your help and insights!

You are right. A frequency multiplier is effectively used to sample the signal. However, I thought it was to extract the data itself once the clock has been extracted. I am not sure it is useful for clock extaction.

I know that the pull range of the vcxo is greater than the frequency range of the bi-phase mark signal. Hence, there should be no problem on this side. There will be plenty of range for the vcxo to track the incoming signal.

If you find the proper way to lock that vcxo on the signal, I should be able to multiply the clock using a DLL and extract the data after that.

Thank you again for your time.

TurboPC

 

[robotman]

biphase mark

Just a note of warning.....

I have done some VCXO/DLL designs in the past. The DLL's are very sensitive to jitter and frequency change. I have even had instances where the DLL just won't recover with a reset, it requires powering down the device. This is not very good.

Anyway, I have heard that the new DCMs are much better. I will know tonight. I am finishing just such a design tonight. I will let you know in the next day or so....

robotman

 

[TurboPC]

clock recovery in biphase

Thanks robotman.

As a coincidence, I have done also some vcxo designs in the past. I confirm also your results regarding DLL and jitters. They don't like each other. On this side, @ltera's pll are much better.

I'll wait for your conclusion...

 

[layes2]

biphase mark recovery circuit

xlinx even can use fpga to implment usb 480Mcdr

 

[Buriedcode]

clock 9 bi

Hi, probably worthless advice, but I would do it purely digital.

I've got a small 32MC CPLD successfully recovering a biphase coded signal at 12Mhz, in simulation it'll work up to 60Mhz (apparently....)

Its pretty damn simple, and I imgine I'm over simplifying it, since you guys are talking about DPLL's and VCO's. You said you need a stable clock, why don't you just use a crystal oscillator at your receiver, most FPGA's have a built in PLL for running at stupidly high frequencies from lower frequency crystals, and since your signal is 24MHz, it's not difficult to find such a crystal, unless your incoming data slowly changes in frequency, then obviously you would need the DPLL to follow it.

Oversample at about 5-8 times the incoming chiprate and setup an edge detector, with a counter. As I'm sure you know biphase has one or two transitions per 'bit', depending on the data, your counter could just look for for regular transitions.

Anyway, again, sorry if I'm over simplifying this, its just I designed mine from a Xilinx app note, in schematic, took me all but 15 minutes, its quite stable, and not particularly sensitive to jitter, since its running of its own clock (not using the signal itself to clock the entire reciever).

Good Luck

BuriedCode.