Implementing a Latch using a Flip Flop ???

[lakshman.ar]

Hi every1,
Can any1 provide me a solution to implement a Latch ( D-Latch) using a Flip-Flop ( DFF).

any combinational gates can be used along with the DFF to implement the functionality of a latch

WBR
lakshman

 

[phutanesv]

what for u need this conversation,

 

[laststep]

this is simple just put an AND gate at the DFF's preset signal and "and " the input signal and clock signal together.
Then put another and gate at the clear signal pin, "and" the invert input signal and also the clock signal.
This assume that, the control signal is active high and we use total of 3 gate: 2 and gates and 1 inverter.

But as phutanesv said, what for we need this conversation.

 

[lakshman.ar]

an interview question.

so now which is the enable signal, still the clk ? or its preset or clear ?

 

[laststep]

enable signal still the preset and also the clear signal just that we are no using the clk and input pin.
Mean we just use the preset and clear pin with the help of and gate and not gate

 

[lakshman.ar]

@laststep : thnk u mate ... the logic works !!!

WBR
Lakshman

 

[srinivas_kamana]

Din = E'Q+INE, Pr = (E'Q+INE)', Cr = E'Q+INE, clock = E.
where Din- input to D-flipflop
E- Enable input,
Q-present state of D-flipflop
IN-input signal
Pr-preset input
Cr-clear input

 

[santoshl]

I think srinivas_kamana design gives a stable result eleimanting glitches during enable transition.

 

[archillios]

how about this?
1. E = CLK'
2. LAT_Q= MUX(IN,DFF_Q),
(select by CLK, if CLK=1'b1, LAT_Q = IN, else LAQ_Q=DFF_Q)
3. LAT_IN = DFF_IN,

 

[arun_prabu]

Whether this will work?

Data to D pin of the FF.

Data -> buf -> Input A of XOR
Data -> buf -> not -> not -> not -> not -> Input B of XOR


Output of XOR -> Input A of AND

Clk -> Input B of AND

Output of AND -> CLK pin of FF

regards,
Arun

 

[kanagavel_docs]

Hi,

Please find the circuit. Correct me if I am worng.


Regards,
Kanagavel. S