10bit SAR ADC

[the8thhabit]

I am currently designing a SAR ADC in cadence that uses a 10bit 20MS/s with monotonic structure. My questions are as follows.

1. When setting the unitcap of the CDAC, is it correct to use MATLAB to figure out the proper unitcap value based on the SNDR I am aiming for?

2. The unit caps in CDAC are very small values in fF, and I was wondering if you draw these unit caps directly when laying out.
And what are some ways to implement it?


I'm designing a SAR ADC for the first time and I'm having a lot of trouble. If you could help me, it would be very helpful. Thank you.


The figure below shows the structure I designed.

 

[sidun.av]

Hi @the8thhabit ,
1. I think that would be the right approach. Usually, we select the unit cap size based on a trade-off between kT/C noise, power consumption, and parasitics. You can roughly estimate parasitics by simulating a unit cap of different sizes across process/MC and then adding it to your Matlab model.
2. My personal opinion here is that since you have quite low precision and speed and if you are not very restricted with area/power consumption, you better go for at least a few tens of fF, because most likely your routing parasitics will dominate in your SNR degradation.
Re the unit caps - just use C1<0>, C2<1:0>, C3<3:0> etc. notation in your schematic to get 1x, 2x, 4x values. In this case it would be easy to do the layout, because every cap will be made of unit caps. After that you may use modgen in Layout XL to do proper matching quickly
Hopefully, that helps.

--- Updated Thursday at 11:45 AM ---

I will also answer some of your questions from the deleted thread:

2. If I set the unitcap value to 5fF, when I try to configure the CDAC using MIM cap, I am unable to implement 5fF because the MIM cap value of MIM cap is greater than 5fF. How should I proceed with the cadence simulation in this case?
- You can probably play around with finger count and spacing in the PCELL, but most likely you are at the limit of the foundry's characterised model of the MIM cap. You should consider this value to be the minimum possible one.

3. If I change the MIM cap option to configure CDAC from 1p0f to 1p7f, the cap area will be smaller, which will increase the variation. In sar adc, the mismatch of CDAC has a big impact on the adc linearity, and I wonder if changing the MIM cap option to 1p7f will not affect the linearity.
- In SAR ADC and SC circuits the absolute values of the capacitors don't matter. Only the relation between them is important. So, if you use unit cap values and do a proper matching, that shouldn't have a big impact on the characteristics of the ADC.

5. I was wondering what the standard is for choosing between MOM and MIM for the caps that make up a CDAC?
- I am not aware of any recommendations about this, but most likely, MOM capacitors will be more asymmetric (bottom plate and top plate parasitics will be different), more sensitive to the substrate noise (because it's closer to it) and probably will have a larger minimum value that MIM. But these MOM caps should be more precise and maybe slightly easier to route.
P.S. MOM capacitors are more effective at larger nodes (180nm, 90nm) whereas MIM is better at lower (40nm, 28nm) because the plate-to-plate capacitance dominates till approx. 65nm and below 65nm the fringe capacitance will dominate.

 

[sidun.av]

I have to correct my previous post - I got confused in terminology.
MOM capacitors are constructed of multiple inter-digitated fingers formed with metal interconnect layers (using fringe capacitance mostly)
MIM capacitors use plate-to-plate capacitance.

So, I have to correct my answer:

5. I was wondering what the standard is for choosing between MOM and MIM for the caps that make up a CDAC?
- I am not aware of any recommendations about this, but most likely, MIM capacitors will be more asymmetric (bottom plate and top plate parasitics will be different), more sensitive to the substrate noise (because it's closer to it) and probably will have a larger minimum value than MOM. But these MIM caps should be more precise and maybe slightly easier to route.
P.S. MIM capacitors are more effective at larger nodes (180nm, 90nm) whereas MOM is better at lower (40nm, 28nm) because the plate-to-plate capacitance dominates till approx. 65nm and below 65nm the fringe capacitance will dominate.

 

[the8thhabit]

I have to correct my previous post - I got confused in terminology.
MOM capacitors are constructed of multiple inter-digitated fingers formed with metal interconnect layers (using fringe capacitance mostly)
MIM capacitors use plate-to-plate capacitance.

So, I have to correct my answer:

5. I was wondering what the standard is for choosing between MOM and MIM for the caps that make up a CDAC?
- I am not aware of any recommendations about this, but most likely, MIM capacitors will be more asymmetric (bottom plate and top plate parasitics will be different), more sensitive to the substrate noise (because it's closer to it) and probably will have a larger minimum value than MOM. But these MIM caps should be more precise and maybe slightly easier to route.
P.S. MIM capacitors are more effective at larger nodes (180nm, 90nm) whereas MOM is better at lower (40nm, 28nm) because the plate-to-plate capacitance dominates till approx. 65nm and below 65nm the fringe capacitance will dominate.

Thank you very much for your answer
I have a few additional questions

1. currently I am using 180nm process, the minimum value of MOM cap provided is 10fF and MIM cap is 17fF.
Therefore, I am designing a SAR ADC with the unit cap set to 10fF using the MOM cap.
In this case, is it correct that I should only use Cu above 10fF for simulation? (I wonder if the minimum unit cap value is determined by the process?)

1.1 In your answer regarding unit cap, you said to use notation values such as C1<0>, C2<1:0> , C3<3:0> in the schematic to get 1X, 2X, 4X values, but how should I apply the notation values if the cap value is sized by fingers and length as shown in the photo below?

2. I understand that to determine the Cu value, I need to simulate the Cu and SNDR relationship in matlab.
However, I am struggling with this process as it is difficult to find information about the code to implement Cu and SNDR in matlab. I was wondering if you have any information you can point me to in this regard.

3. Also, I am currently simulating a SAR ADC of 10bit with a supply voltage of 1.8v and I have found that the FFT simulation shows that the SNR and SNDR are the same (49.83dB).
However, I noticed that the ENOB is very low at 7.9bit.
When I saw this result, I thought that since SNR and SNDR are the same, there is no distortion, so the linearity such as INL, DNL is okay, so I thought that I should improve it in terms of noise, not linearity.
So I need to reduce the thermal noise, quantization noise, comparator noise to improve the noise.
I would like to ask what circuit should be fixed to improve these noises and if I am right in the direction I thought.

 

[sidun.av]

1. You are right, you should set 10fF as a minimum unit cap size for your Matlab simulations. Generally speaking, yes 10fF is the process limitation for you as a designer.
1.1. Fingers and length will specify your unit cap value and geometry in layout. Simply configure your unit capacitor size through fingers and length to achieve desired value of capacitance and then use <> notation in the instance name, as shown below. This notation simply means specified number of instances in parallel, for example:
C6<1:0> = C6<1> || C6<0> -> 2x C6 in parallel
C6<3:0> = C6<3> || C6<2> || C6<1> || C6<0> -> 4x C6 in parallel

2. I have a few ways in mind:

1. Calculate your CDAC transfer function and add the corresponding deltaC to each capacitor in your equation. Build a complete model of SAR ADC in Matlab Simulink, using ideal elements for comparator logic etc. and place your CDAC as a transfer function block. After that, you can simulate it like a normal circuit, varying deltaC and estimating the impact on the output.
2. Build an ideal model directly in Cadence, using Verilog-A models and ideal components for comparator, logic etc. In this case, you can use your CDAC as a circuit and perform variation using Cadence. The benefit of that approach is that after you're satisfied with the schematic results, you can do the layout of CDAC, extract it and estimate the impact on your SNR/INL etc. The downside is that this approach would be quite slower to simulate rather than Matlab, but it is all depends on your computational capacity

I cannot suggest any resources straight away, but I will add them to my post later.

3. It's quite hard to guess without seeing your schematic and test setup.

• You are thinking that it is a noise issue - are you simulating your ADC with transient noise on? What bandwidth of noise are you using? If you are not using these settings, then your circuit is absolutely noiseless and the issue is something else.
• You need to make sure that in your simulation you are using the correct number of samples and sim time to avoid FFT leakage (you can read more about this in this book: Understanding digital signal processing by Richard G. Lyons). As a sanity check, you can export your sim data to .csv and use FFT in MATLAB to verify your results.
  

 

[the8thhabit]

1. You are right, you should set 10fF as a minimum unit cap size for your Matlab simulations. Generally speaking, yes 10fF is the process limitation for you as a designer.
1.1. Fingers and length will specify your unit cap value and geometry in layout. Simply configure your unit capacitor size through fingers and length to achieve desired value of capacitance and then use <> notation in the instance name, as shown below. This notation simply means specified number of instances in parallel, for example:
C6<1:0> = C6<1> || C6<0> -> 2x C6 in parallel
C6<3:0> = C6<3> || C6<2> || C6<1> || C6<0> -> 4x C6 in parallel

View attachment 196495
2. I have a few ways in mind:

1. Calculate your CDAC transfer function and add the corresponding deltaC to each capacitor in your equation. Build a complete model of SAR ADC in Matlab Simulink, using ideal elements for comparator logic etc. and place your CDAC as a transfer function block. After that, you can simulate it like a normal circuit, varying deltaC and estimating the impact on the output.
2. Build an ideal model directly in Cadence, using Verilog-A models and ideal components for comparator, logic etc. In this case, you can use your CDAC as a circuit and perform variation using Cadence. The benefit of that approach is that after you're satisfied with the schematic results, you can do the layout of CDAC, extract it and estimate the impact on your SNR/INL etc. The downside is that this approach would be quite slower to simulate rather than Matlab, but it is all depends on your computational capacity

I cannot suggest any resources straight away, but I will add them to my post later.

3. It's quite hard to guess without seeing your schematic and test setup.

• You are thinking that it is a noise issue - are you simulating your ADC with transient noise on? What bandwidth of noise are you using? If you are not using these settings, then your circuit is absolutely noiseless and the issue is something else.
• You need to make sure that in your simulation you are using the correct number of samples and sim time to avoid FFT leakage (you can read more about this in this book: Understanding digital signal processing by Richard G. Lyons). As a sanity check, you can export your sim data to .csv and use FFT in MATLAB to verify your results.

1. You are right, you should set 10fF as a minimum unit cap size for your Matlab simulations. Generally speaking, yes 10fF is the process limitation for you as a designer.
1.1. Fingers and length will specify your unit cap value and geometry in layout. Simply configure your unit capacitor size through fingers and length to achieve desired value of capacitance and then use <> notation in the instance name, as shown below. This notation simply means specified number of instances in parallel, for example:
C6<1:0> = C6<1> || C6<0> -> 2x C6 in parallel
C6<3:0> = C6<3> || C6<2> || C6<1> || C6<0> -> 4x C6 in parallel

View attachment 196495
2. I have a few ways in mind:

1. Calculate your CDAC transfer function and add the corresponding deltaC to each capacitor in your equation. Build a complete model of SAR ADC in Matlab Simulink, using ideal elements for comparator logic etc. and place your CDAC as a transfer function block. After that, you can simulate it like a normal circuit, varying deltaC and estimating the impact on the output.
2. Build an ideal model directly in Cadence, using Verilog-A models and ideal components for comparator, logic etc. In this case, you can use your CDAC as a circuit and perform variation using Cadence. The benefit of that approach is that after you're satisfied with the schematic results, you can do the layout of CDAC, extract it and estimate the impact on your SNR/INL etc. The downside is that this approach would be quite slower to simulate rather than Matlab, but it is all depends on your computational capacity

I cannot suggest any resources straight away, but I will add them to my post later.

3. It's quite hard to guess without seeing your schematic and test setup.

• You are thinking that it is a noise issue - are you simulating your ADC with transient noise on? What bandwidth of noise are you using? If you are not using these settings, then your circuit is absolutely noiseless and the issue is something else.
• You need to make sure that in your simulation you are using the correct number of samples and sim time to avoid FFT leakage (you can read more about this in this book: Understanding digital signal processing by Richard G. Lyons). As a sanity check, you can export your sim data to .csv and use FFT in MATLAB to verify your results.

Thanks for your reply!
Your answer is really helpful to me!!

1. So when you say that it's much easier to layout using unit cap and implementing cap C6<1:0> like this, does that mean it's easier to layout using common centroid + dummy cap layout method?
(As far as I know, common centroid and dummy cap layout is a well-known CDAC layout method, given the CDAC mismatch).

2. thank you so much!

3. Below is the result of FFT simulation, the input sin wave frequency is 0.605MHz and the sampling rate is 20MS/s. The sampling count is 1024 and the waveform is shown up to 10MHz as shown in the figure. I would be very grateful if you could answer my previous question again.

Am I understanding the FFT simulation correctly and if so, I was wondering if it is correct to increase the ENOB in terms of noise since there is no distortion in this case.

 

[sidun.av]

1. That's correct.
2. Hopefully, that helps
3. Your simulation setup seems fine to me:
fin = 0.605 MHz;
N = 1024;
fs = 20 MHz;

Tsim = 52us - 800ns = 51.2 us;
Tin = 1/fin = 1.652 us;
Nperiods =Tsim / Tin = 30.976 periods, nearly 31 (integer number of input signal period, looks ok)
FFT resolution = fs / N = 20 MHz / 1024 = 19.531 kHz
fin / FFT resolution = 31 (input signal energy falls in one bin, looks ok)

As far as I can see, the distortion is the problem here. Try to understand which block is the biggest contributor to these harmonics, by replacing them with ideal models, one by one. One more thing that came into my mind is to check if you are using a strobe period while simulating your ADC to achieve evenly spaced samples:

https://community.cadence.com/caden...re-tech-tips-using-the-spectre-strobe-feature

If you are not using this, then it may lead to worse FFT results. Also check that your accuracy preset in simulator is conservative (conservative option in ADEL or CX for Spectre X in ADEXL/Maestro and don't use aps++ option)

x

 

[the8thhabit]

1. That's correct.
2. Hopefully, that helps
3. Your simulation setup seems fine to me:
fin = 0.605 MHz;
N = 1024;
fs = 20 MHz;

Tsim = 52us - 800ns = 51.2 us;
Tin = 1/fin = 1.652 us;
Nperiods =Tsim / Tin = 30.976 periods, nearly 31 (integer number of input signal period, looks ok)
FFT resolution = fs / N = 20 MHz / 1024 = 19.531 kHz
fin / FFT resolution = 31 (input signal energy falls in one bin, looks ok)

As far as I can see, the distortion is the problem here. Try to understand which block is the biggest contributor to these harmonics, by replacing them with ideal models, one by one. One more thing that came into my mind is to check if you are using a strobe period while simulating your ADC to achieve evenly spaced samples:

https://community.cadence.com/caden...re-tech-tips-using-the-spectre-strobe-feature

If you are not using this, then it may lead to worse FFT results. Also check that your accuracy preset in simulator is conservative (conservative option in ADEL or CX for Spectre X in ADEXL/Maestro and don't use aps++ option)


View attachment 196500
x

Thanks for the answer!

1. So the reason for the low ENOB with such a low SNDR is due to the distorted harmonic component as shown?
As I understand it, if the FFT simulation shows that the SNR and SNDR are the same, it means that there is no distortion, so I thought it was suppressing the noise, not the distortion, that would increase the ENOB in that simulation.

2. If the distorted harmonic component is the cause of the low ENOB, then why are the SNR and SNDR the same?

 

[sidun.av]

I think that the problem here is Cadence FFT settings. If you look at THD - it shows 0% meaning that you have no distortion at all. I really doubt it can be real, unless your circuit is ideal. THD = 0 indicates that Spectrum analyser simply cannot see harmonics of your signal (that contributes to SNDR) and considering all harmonics apart from your signal harmonic to be noise. That's why your SNR = SNDR.

Here are some formulas to help you understand better:
SINAD_Power = (sum of all powers in FFT array) - FundamentalPower.
SNR:
Noise_Power = SINAD_Power - Harm_Power
SNR = 10 * log10( FundamentalPower / Noise_Power)